499 lines
18 KiB
C
499 lines
18 KiB
C
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/*
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* parallel.h Parallel port definitions
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*
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* =========================================================================
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*
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* Open Watcom Project
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*
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* Copyright (c) 2004-2010 The Open Watcom Contributors. All Rights Reserved.
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*
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* This file is automatically generated. Do not edit directly.
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*
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* =========================================================================
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*/
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#ifndef _PARALLEL_
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#define _PARALLEL_
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#ifndef _ENABLE_AUTODEPEND
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#pragma read_only_file;
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#endif
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#include <parallel.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Parallel port device name */
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#define DD_PARALLEL_PORT_BASE_NAME_U L"ParallelPort"
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/* Daisy-chain maximum identifier */
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#define IEEE_1284_3_DAISY_CHAIN_MAX_ID 3
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/* Parallel port internal device I/O control codes */
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#define IOCTL_INTERNAL_PARALLEL_PORT_ALLOCATE \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 11, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_GET_PARALLEL_PORT_INFO \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 12, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_PARALLEL_CONNECT_INTERRUPT \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 13, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_PARALLEL_DISCONNECT_INTERRUPT \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 14, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_RELEASE_PARALLEL_PORT_INFO \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 15, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_GET_MORE_PARALLEL_PORT_INFO \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 17, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_PARCHIP_CONNECT \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 18, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_PARALLEL_SET_CHIP_MODE \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 19, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_PARALLEL_CLEAR_CHIP_MODE \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 20, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_GET_PARALLEL_PNP_INFO \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 21, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_INIT_1284_3_BUS \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 22, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_SELECT_DEVICE \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 23, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_DESELECT_DEVICE \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 24, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#if (NTDDI_VERSION >= 0x05010000)
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#define IOCTL_INTERNAL_GET_PARPORT_FDO \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 29, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#endif
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#define IOCTL_INTERNAL_PARCLASS_CONNECT \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 30, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_PARCLASS_DISCONNECT \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 31, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_DISCONNECT_IDLE \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 32, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_LOCK_PORT \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 37, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_UNLOCK_PORT \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 38, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_PARALLEL_PORT_FREE \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 40, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_PARDOT3_CONNECT \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 41, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_PARDOT3_DISCONNECT \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 42, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_PARDOT3_RESET \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 43, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_PARDOT3_SIGNAL \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 44, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_REGISTER_FOR_REMOVAL_RELATIONS \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 50, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_UNREGISTER_FOR_REMOVAL_RELATIONS \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 51, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#if (NTDDI_VERSION >= 0x05010000)
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#define IOCTL_INTERNAL_LOCK_PORT_NO_SELECT \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 52, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_UNLOCK_PORT_NO_SELECT \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 53, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_DISABLE_END_OF_CHAIN_BUS_RESCAN \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 54, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#define IOCTL_INTERNAL_ENABLE_END_OF_CHAIN_BUS_RESCAN \
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CTL_CODE( FILE_DEVICE_PARALLEL_PORT, 55, METHOD_BUFFERED, FILE_ANY_ACCESS )
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#endif
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/* Mode qualifier lengths */
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#define MODE_LEN_1284_3 7
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#define LEGACYZIP_MODE_LEN 3
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/* 1284.3 commands */
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#define CPP_ASSIGN_ADDR 0x00
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#define CPP_SELECT 0xE0
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#define CPP_DESELECT 0x30
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#define CPP_QUERY_INT 0x08
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#define CPP_DISABLE_INT 0x40
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#define CPP_ENABLE_INT 0x48
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#define CPP_CLEAR_INT_LAT 0x50
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#define CPP_SET_INT_LAT 0x58
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#define CPP_COMMAND_FILTER 0xF8
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/* Parallel port hardware capability flags */
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#define PPT_NO_HARDWARE_PRESENT 0x00000000L
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#define PPT_ECP_PRESENT 0x00000001L
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#define PPT_EPP_PRESENT 0x00000002L
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#define PPT_EPP_32_PRESENT 0x00000004L
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#define PPT_BYTE_PRESENT 0x00000008L
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#define PPT_BIDI_PRESENT 0x00000008L
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#define PPT_1284_3_PRESENT 0x00000010L
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/* Parallel port command flags */
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#define PAR_END_OF_CHAIN_DEVICE 0x00000001L
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#define PAR_HAVE_PORT_KEEP_PORT 0x00000002L
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#define PAR_LEGACY_ZIP_DRIVE 0x00000004L
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#define PAR_LEGACY_ZIP_DRIVE_STD_MODE 0x00000010L
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#define PAR_LEGACY_ZIP_DRIVE_EPP_MODE 0x00000020L
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/* 1284.3 identifiers */
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#define DOT3_END_OF_CHAIN_ID 4
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#define DOT3_LEGACY_ZIP_ID 5
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/* Parallel port hardware modes */
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#define INITIAL_MODE 0x00000000L
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/* Parallel chip flag */
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#define PARCHIP_ECR_ARBITRATOR 1
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/* Offset constants */
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#define DATA_OFFSET 0
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#define OFFSET_ECP_AFIFO 0x0000
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#define AFIFO_OFFSET OFFSET_ECP_AFIFO
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#define DSR_OFFSET 1
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#define DCR_OFFSET 2
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#define EPP_OFFSET 4
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#ifndef DVRH_USE_PARPORT_ECP_ADDR
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#define DVRH_USE_PARPORT_ECP_ADDR 0
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#endif
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#if !DVRH_USE_PARPORT_ECP_ADDR
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#define ECP_OFFSET 0x0400
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#define CNFGB_OFFSET 0x0401
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#define ECR_OFFSET 0x0402
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#else
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#define ECP_OFFSET 0x0000
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#define CNFGB_OFFSET 0x0001
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#define ECR_OFFSET 0x0002
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#endif
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#define FIFO_OFFSET ECP_OFFSET
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#define CFIFO_OFFSET ECP_OFFSET
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#define CNFGA_OFFSET ECP_OFFSET
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#define ECP_DFIFO_OFFSET ECP_OFFSET
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#define TFIFO_OFFSET ECP_OFFSET
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#define OFFSET_ECP_DFIFO ECP_OFFSET
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#define OFFSET_TFIFO ECP_OFFSET
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#define OFFSET_CFIFO ECP_OFFSET
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#define OFFSET_ECR ECP_OFFSET
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#define OFFSET_PARALLEL_REGISTER_SPAN 0x0003
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/* Span constants */
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#define ECP_SPAN 3
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#define EPP_SPAN 4
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/* DSR flags */
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#define DSR_NOT_BUSY 0x80
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#define DSR_NOT_ACK 0x40
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#define DSR_PERROR 0x20
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#define DSR_SELECT 0x10
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#define DSR_NOT_FAULT 0x08
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#define DSR_NOT_PTR_BUSY 0x80
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#define DSR_NOT_PERIPH_ACK 0x80
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#define DSR_WAIT 0x80
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#define DSR_PTR_CLK 0x40
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#define DSR_PERIPH_CLK 0x40
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#define DSR_INTR 0x40
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#define DSR_ACK_DATA_REQ 0x20
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#define DSR_NOT_ACK_REVERSE 0x20
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#define DSR_XFLAG 0x10
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#define DSR_NOT_DATA_AVAIL 0x08
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#define DSR_NOT_PERIPH_REQUEST 0x08
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/* DCR flags */
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#define DCR_DIRECTION 0x20
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#define DCR_ACKINT_ENABLED 0x10
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#define DCR_SELECT_IN 0x08
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#define DCR_NOT_INIT 0x04
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#define DCR_AUTOFEED 0x02
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#define DCR_STROBE 0x01
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#define DCR_NOT_1284_ACTIVE 0x08
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#define DCR_ASTRB 0x08
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#define DCR_NOT_REVERSE_REQUEST 0x04
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#define DCR_NULL 0x04
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#define DCR_NOT_HOST_BUSY 0x02
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#define DCR_NOT_HOST_ACK 0x02
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#define DCR_DSTRB 0x02
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#define DCR_NOT_HOST_CLK 0x01
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#define DCR_WRITE 0x01
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/* Configuration register A flags */
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#define CNFGA_IMPID_MASK 0x70
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#define CNFGA_IMPID_16BIT 0x00
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#define CNFGA_IMPID_8BIT 0x10
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#define CNFGA_IMPID_32BIT 0x20
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#define CNFGA_NO_TRANS_BYTE 0x04
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#define CNFGA_IMPID_MASK 0x70
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#define CNFGA_IMPID_SHIFT 4
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/* Default ECR values */
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#if !PARCHIP_ECR_ARBITRATOR
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#define DEFAULT_ECR_PS2 0x34
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#define DEFAULT_ECR_ECP 0x74
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#endif
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#define DEFAULT_ECR_TEST 0xD4
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#define DEFAULT_ECR_COMPATIBILITY 0x14
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#define DEFAULT_ECR_CONFIGURATION 0xF4
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/* ECR flags */
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#define ECR_ERRINT_DISABLED 0x10
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#define ECR_DMA_ENABLED 0x08
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#define ECR_SVC_INT_DISABLED 0x04
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#define ECR_MODE_MASK 0x1F
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#define ECR_SPP_MODE 0x00
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#define ECR_BYTE_MODE 0x20
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#define ECR_BYTE_PIO_MODE \
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(ECR_BYTE_MODE | ECR_ERRINT_DISABLED | ECR_SVC_INT_DISABLED)
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#define ECR_FASTCENT_MODE 0x40
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#define ECR_ECP_MODE 0x60
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#define ECR_ECP_PIO_MODE \
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(ECR_ECP_MODE | ECR_ERRINT_DISABLED | ECR_SVC_INT_DISABLED)
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#define ECR_EPP_MODE 0x80
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#define ECR_EPP_PIO_MODE \
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(ECR_EPP_MODE | ECR_ERRINT_DISABLED | ECR_SVC_INT_DIABLED)
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#define ECR_RESERVED_MODE 0x10
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#define ECR_TEST_MODE 0xC0
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#define ECR_CONFIG_MODE 0xE0
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#define ECR_FIFO_MASK 0x03
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#define ECR_FIFO_FULL 0x02
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#define ECR_FIFO_EMPTY 0x01
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#define ECR_FIFO_SOME_DATA 0x00
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#define ECP_MAX_FIFO_DEPTH 4098
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/* FIFO constants */
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#define FIFO_PWORD_8BIT 1
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#define FIFO_PWORD_16BIT 0
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#define FIFO_PWORD_32BIT 2
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/* Bit shifts */
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#define BIT_7 7
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#define BIT_6 6
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#define BIT_5 5
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#define BIT_4 4
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#define BIT_3 3
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#define BIT_2 2
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#define BIT_1 1
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#define BIT_0 0
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/* Bit set flags */
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#define BIT_7_SET 0x80
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#define BIT_6_SET 0x40
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#define BIT_5_SET 0x20
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#define BIT_4_SET 0x10
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#define BIT_3_SET 0x08
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#define BIT_2_SET 0x04
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#define BIT_1_SET 0x02
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#define BIT_0_SET 0x01
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/* Directions */
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#define DIR_READ 1
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#define DIR_WRITE 0
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/* IRQ enable values */
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#define IRQEN_ENABLE 1
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#define IRQEN_DISABLE 0
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/* Activity values */
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#define ACTIVE 1
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#define INACTIVE 0
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#define DONT_CARE 2
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/* DVRH constants */
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#define DVRH_USE_FAST_MACROS 1
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#define DVRH_USE_NIBBLE_MACROS 1
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/* Parallel port removal relations */
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typedef struct _PARPORT_REMOVAL_RELATIONS {
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PDEVICE_OBJECT DeviceObject;
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ULONG Flags;
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PUNICODE_STRING DeviceName;
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} PARPORT_REMOVAL_RELATIONS;
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typedef PARPORT_REMOVAL_RELATIONS *PPARPORT_REMOVAL_RELATIONS;
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/* 1284.3 DL modes */
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typedef enum {
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P12843DL_OFF = 0,
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P12843DL_DOT3_DL = 1,
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P12843DL_MLC_DL = 2,
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P12843DL_DOT4_DL = 3
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} P12843_DL_MODES;
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/* Parallel port callbacks */
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typedef BOOLEAN (NTAPI *PPARALLEL_TRY_ALLOCATE_ROUTINE)( PVOID );
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typedef VOID (NTAPI *PPARALLEL_FREE_ROUTINE)( PVOID );
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typedef ULONG (NTAPI *PPARALLEL_QUERY_WAITERS_ROUTINE)( PVOID );
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typedef NTSTATUS (NTAPI *PPARALLEL_SET_CHIP_MODE)( PVOID, UCHAR );
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typedef NTSTATUS (NTAPI *PPARALLEL_CLEAR_CHIP_MODE)( PVOID, UCHAR );
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typedef NTSTATUS (NTAPI *PPARALLEL_TRY_SELECT_ROUTINE)( PVOID, PVOID );
|
||
|
|
typedef NTSTATUS (NTAPI *PPARALLEL_DESELECT_ROUTINE)( PVOID, PVOID );
|
||
|
|
typedef NTSTATUS (NTAPI *PPARCHIP_SET_CHIP_MODE)( PVOID, UCHAR );
|
||
|
|
typedef NTSTATUS (NTAPI *PPARCHIP_CLEAR_CHIP_MODE)( PVOID, UCHAR );
|
||
|
|
typedef VOID (NTAPI *PPARALLEL_DEFERRED_ROUTINE)( PVOID );
|
||
|
|
|
||
|
|
/* Parallel chip information */
|
||
|
|
typedef struct _PARALLEL_PARCHIP_INFO {
|
||
|
|
PUCHAR Controller;
|
||
|
|
PUCHAR EcrController;
|
||
|
|
ULONG HardwareModes;
|
||
|
|
PPARCHIP_SET_CHIP_MODE ParChipSetMode;
|
||
|
|
PPARCHIP_CLEAR_CHIP_MODE ParChipClearMode;
|
||
|
|
PVOID Context;
|
||
|
|
BOOLEAN success;
|
||
|
|
} PARALLEL_PARCHIP_INFO;
|
||
|
|
typedef PARALLEL_PARCHIP_INFO *PPARALLEL_PARCHIP_INFO;
|
||
|
|
|
||
|
|
/* Parallel port information */
|
||
|
|
typedef struct _PARALLEL_PORT_INFORMATION {
|
||
|
|
PHYSICAL_ADDRESS OriginalController;
|
||
|
|
PUCHAR Controller;
|
||
|
|
ULONG SpanOfController;
|
||
|
|
PPARALLEL_TRY_ALLOCATE_ROUTINE TryAllocatePort;
|
||
|
|
PPARALLEL_FREE_ROUTINE FreePort;
|
||
|
|
PPARALLEL_QUERY_WAITERS_ROUTINE QueryNumWaiters;
|
||
|
|
PVOID Context;
|
||
|
|
} PARALLEL_PORT_INFORMATION;
|
||
|
|
typedef PARALLEL_PORT_INFORMATION *PPARALLEL_PORT_INFORMATION;
|
||
|
|
|
||
|
|
/* Parallel port Plug and Play information */
|
||
|
|
typedef struct _PARALLEL_PNP_INFORMATION {
|
||
|
|
PHYSICAL_ADDRESS OriginalEcpController;
|
||
|
|
PUCHAR EcpController;
|
||
|
|
ULONG SpanOfEcpController;
|
||
|
|
ULONG PortNumber;
|
||
|
|
ULONG HardwareCapabilities;
|
||
|
|
PPARALLEL_SET_CHIP_MODE TrySetChipMode;
|
||
|
|
PPARALLEL_CLEAR_CHIP_MODE ClearChipMode;
|
||
|
|
ULONG FifoDepth;
|
||
|
|
ULONG FifoWidth;
|
||
|
|
PHYSICAL_ADDRESS EppControllerPhysicalAddress;
|
||
|
|
ULONG SpanOfEppController;
|
||
|
|
ULONG Ieee1284_3DeviceCount;
|
||
|
|
PPARALLEL_TRY_SELECT_ROUTINE TrySelectDevice;
|
||
|
|
PPARALLEL_DESELECT_ROUTINE DeselectDevice;
|
||
|
|
PVOID Context;
|
||
|
|
ULONG CurrentMode;
|
||
|
|
PWSTR PortName;
|
||
|
|
} PARALLEL_PNP_INFORMATION;
|
||
|
|
typedef PARALLEL_PNP_INFORMATION *PPARALLEL_PNP_INFORMATION;
|
||
|
|
|
||
|
|
/* Parallel port 1284.3 command */
|
||
|
|
typedef struct _PARALLEL_1284_COMMAND {
|
||
|
|
UCHAR ID;
|
||
|
|
UCHAR Port;
|
||
|
|
ULONG CommandFlags;
|
||
|
|
} PARALLEL_1284_COMMAND;
|
||
|
|
typedef PARALLEL_1284_COMMAND *PPARALLEL_1284_COMMAND;
|
||
|
|
|
||
|
|
/* Parallel chip modes */
|
||
|
|
typedef struct _PARALLEL_CHIP_MODE {
|
||
|
|
UCHAR ModeFlags;
|
||
|
|
BOOLEAN success;
|
||
|
|
} PARALLEL_CHIP_MODE;
|
||
|
|
typedef PARALLEL_CHIP_MODE *PPARALLEL_CHIP_MODE;
|
||
|
|
|
||
|
|
/* Parallel interrupt service routine */
|
||
|
|
typedef struct _PARALLEL_INTERRUPT_SERVICE_ROUTINE {
|
||
|
|
PKSERVICE_ROUTINE InterruptServiceRoutine;
|
||
|
|
PVOID InterruptServiceContext;
|
||
|
|
PPARALLEL_DEFERRED_ROUTINE DeferredPortCheckRoutine;
|
||
|
|
PVOID DeferredPortCheckContext;
|
||
|
|
} PARALLEL_INTERRUPT_SERVICE_ROUTINE;
|
||
|
|
typedef PARALLEL_INTERRUPT_SERVICE_ROUTINE *PPARALLEL_INTERRUPT_SERVICE_ROUTINE;
|
||
|
|
|
||
|
|
/* Parallel interrupt information */
|
||
|
|
typedef struct _PARALLEL_INTERRUPT_INFORMATION {
|
||
|
|
PKINTERRUPT InterruptObject;
|
||
|
|
PPARALLEL_TRY_ALLOCATE_ROUTINE TryAllocatePortAtInterruptLevel;
|
||
|
|
PPARALLEL_FREE_ROUTINE FreePortFromInterruptLevel;
|
||
|
|
PVOID Context;
|
||
|
|
} PARALLEL_INTERRUPT_INFORMATION;
|
||
|
|
typedef PARALLEL_INTERRUPT_INFORMATION *PPARALLEL_INTERRUPT_INFORMATION;
|
||
|
|
|
||
|
|
/* More parallel port information */
|
||
|
|
typedef struct _MORE_PARALLEL_PORT_INFORMATION {
|
||
|
|
INTERFACE_TYPE InterfaceType;
|
||
|
|
ULONG BusNumber;
|
||
|
|
ULONG InterruptLevel;
|
||
|
|
ULONG InterruptVector;
|
||
|
|
KAFFINITY InterruptAffinity;
|
||
|
|
KINTERRUPT_MODE IntteruptMode;
|
||
|
|
} MORE_PARALLEL_PORT_INFORMATION;
|
||
|
|
typedef MORE_PARALLEL_PORT_INFORMATION *PMORE_PARALLEL_PORT_INFORMATION;
|
||
|
|
|
||
|
|
/* Parallel port safety values */
|
||
|
|
typedef enum {
|
||
|
|
SAFE_MODE = 0,
|
||
|
|
UNSAFE_MODE = 1
|
||
|
|
} PARALLEL_SAFETY;
|
||
|
|
|
||
|
|
/* Parallel class callbacks */
|
||
|
|
#define OLD_PARCLASS 0
|
||
|
|
typedef USHORT (NTAPI *PDETERMINE_IEEE_MODES)( PVOID );
|
||
|
|
typedef NTSTATUS (NTAPI *PNEGOTIATE_IEEE_MODE)( PVOID, USHORT, USHORT, PARALLEL_SAFETY, BOOLEAN );
|
||
|
|
typedef NTSTATUS (NTAPI *PTERMINATE_IEEE_MODE)( PVOID );
|
||
|
|
typedef NTSTATUS (NTAPI *PPARALLEL_IEEE_FWD_TO_REV)( PVOID );
|
||
|
|
typedef NTSTATUS (NTAPI *PPARALLEL_IEEE_REV_TO_FWD)( PVOID );
|
||
|
|
typedef NTSTATUS (NTAPI *PPARALLEL_READ)( PVOID, PVOID, ULONG, PULONG, UCHAR );
|
||
|
|
typedef NTSTATUS (NTAPI *PPARALLEL_WRITE)( PVOID, PVOID, ULONG, PULONG, UCHAR );
|
||
|
|
typedef NTSTATUS (NTAPI *PPARALLEL_TRYSELECT_DEVICE)( PVOID, PARALLEL_1284_COMMAND );
|
||
|
|
typedef NTSTATUS (NTAPI *PPARALLEL_DESELECT_DEVICE)( PVOID, PARALLEL_1284_COMMAND );
|
||
|
|
|
||
|
|
/* Parallel class information */
|
||
|
|
typedef struct _PARCLASS_INFORMATION {
|
||
|
|
PUCHAR Controller;
|
||
|
|
PUCHAR EcrController;
|
||
|
|
ULONG SpanOfController;
|
||
|
|
PDETERMINE_IEEE_MODES DetermineIeeeModes;
|
||
|
|
PNEGOTIATE_IEEE_MODE NegotiateIeeeMode;
|
||
|
|
PTERMINATE_IEEE_MODE TerminateIeeeMode;
|
||
|
|
PPARALLEL_IEEE_FWD_TO_REV IeeeFwdToRevMode;
|
||
|
|
PPARALLEL_IEEE_REV_TO_FWD IeeeRevToFwdMode;
|
||
|
|
PPARALLEL_READ ParallelRead;
|
||
|
|
PPARALLEL_WRITE ParallelWrite;
|
||
|
|
PVOID ParclassContext;
|
||
|
|
ULONG HardwareCapabilities;
|
||
|
|
ULONG FifoDepth;
|
||
|
|
ULONG FifoWidth;
|
||
|
|
PPARALLEL_TRYSELECT_DEVICE ParallelTryselect;
|
||
|
|
PPARALLEL_DESELECT_DEVICE ParallelDeSelect;
|
||
|
|
} PARCLASS_INFORMATION;
|
||
|
|
typedef PARCLASS_INFORMATION *PPARCLASS_INFORMATION;
|
||
|
|
|
||
|
|
/* 1284.3 phases */
|
||
|
|
typedef enum {
|
||
|
|
PHASE_UNKNOWN = 0,
|
||
|
|
PHASE_NEGOTIATION = 1,
|
||
|
|
PHASE_SETUP = 2,
|
||
|
|
PHASE_FORWARD_IDLE = 3,
|
||
|
|
PHASE_FORWARD_XFER = 4,
|
||
|
|
PHASE_FWD_TO_REV = 5,
|
||
|
|
PHASE_REVERSE_IDLE = 6,
|
||
|
|
PHASE_REVERSE_XFER = 7,
|
||
|
|
PHASE_REV_TO_FWD = 8,
|
||
|
|
PHASE_TERMINATE = 9,
|
||
|
|
PHASE_DATA_AVAILABLE = 10,
|
||
|
|
PHASE_DATA_NOT_AVAIL = 11,
|
||
|
|
PHASE_INTERRUPT_HOST = 12
|
||
|
|
} P1284_PHASE;
|
||
|
|
|
||
|
|
/* 1284.3 hardware modes */
|
||
|
|
typedef enum {
|
||
|
|
HW_MODE_COMPATIBILITY = 0,
|
||
|
|
HW_MODE_PS2 = 1,
|
||
|
|
HW_MODE_FAST_CENTRONICS = 2,
|
||
|
|
HW_MODE_ECP = 3,
|
||
|
|
HW_MODE_EPP = 4,
|
||
|
|
HW_MODE_TEST = 6,
|
||
|
|
HW_MODE_CONFIGURATION = 7
|
||
|
|
} P1284_HW_MODE;
|
||
|
|
|
||
|
|
/* Mode qualifiers */
|
||
|
|
static UCHAR ModeQualifier[MODE_LEN_1284_3] =
|
||
|
|
{ 0xAA, 0x55, 0x00, 0xFF, 0x87, 0x78, 0xFF };
|
||
|
|
static UCHAR LegacyZipModeQualifier[LEGACYZIP_MODE_LEN] =
|
||
|
|
{ 0x00, 0x3C, 0x20 };
|
||
|
|
|
||
|
|
/* Other macros */
|
||
|
|
#define TEST_ECR_FIFO( p1, p2 ) (((p1) & ECR_FIFO_MASK) == (p2))
|
||
|
|
#define SET_DCR( p1, p2, p3, p4, p5, p6 ) \
|
||
|
|
((UCHAR)(((p1) == ACTIVE ? BIT_5_SET : 0) | \
|
||
|
|
((p2) == ACTIVE ? BIT_4_SET : 0) | ((p3) == ACTIVE ? 0 : BIT_3_SET) | \
|
||
|
|
((p4) == ACTIVE ? BIT_2_SET : 0) | ((p5) == ACTIVE ? 0 : BIT_1_SET) | \
|
||
|
|
((p6) == ACTIVE ? 0 : BIT_0_SET)))
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
} /* extern "C" */
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* _PARALLEL_ */
|