43 lines
972 B
Plaintext
43 lines
972 B
Plaintext
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--
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-- Sample preview code
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity shiftregister is
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generic
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(
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left : boolean := false -- so shift right
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)
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port
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(
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clk : in std_logic;
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rst : in std_logic;
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en : in std_logic;
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d : in std_logic
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q : out std_logic_vector
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);
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end shiftregister;
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architecture behavioral of shiftregister is
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constant crcpoly : std_logic_vector(7 downto 0) := x"8D";
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type utxstates is (idle, data, parity, stop);
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signal utxstate : utxstates;
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begin
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shift: process ( rst, clk ) begin
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if rst = '1' then
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q <= (others => '0');
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elsif clk'event and clk = '1' then
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if left then
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q <= q(q'left - 1 downto q'right) & d;
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else
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q <= d & q(q'left downto q'right + 1);
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end if;
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end if;
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end process;
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end behavioral;
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