114 lines
4.4 KiB
XML
114 lines
4.4 KiB
XML
<?xml version="1.0"?>
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<!DOCTYPE CodeBlocks_lexer_properties>
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<CodeBlocks_lexer_properties>
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<Lexer name="Verilog"
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index="56"
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filemasks="*.v,*.verilog">
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<!-- #define wxSCI_V_DEFAULT 0 -->
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<Style name="Default"
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index="0"
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fg="0,0,0"
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bg="255,255,255"
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bold="0"
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italics="0"
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underlined="0" />
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<!--#define wxSCI_V_COMMENT 1
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#define wxSCI_V_COMMENTLINE 2
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#define wxSCI_V_COMMENTLINEBANG 3-->
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<Style name="Comment"
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index="1,2,3"
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fg="34,138,34" />
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<!--#define wxSCI_V_NUMBER 4-->
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<Style name="Number"
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index="4"
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fg="160,882,45" />
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<!--fg="240,0,240"/-->
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<!--#define wxSCI_V_STRING 6
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#define wxSCI_V_STRINGEOL 12-->
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<Style name="String"
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index="6,12"
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fg="0,0,255" />
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<!--#define wxSCI_V_OPERATOR 10-->
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<Style name="Operator"
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index="10"
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fg="0,0,128"
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bold="1" />
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<!-- #define wxSCI_V_PREPROCESSOR 9 -->
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<Style name="Preprocessor"
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index="9"
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fg="128,64,0" />
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<!--#define wxSCI_V_IDENTIFIER 11-->
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<Style name="Identifier"
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index="11"
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fg="0,0,0" />
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<!-- #define wxSCI_V_WORD 5 -->
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<Style name="Instructions"
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index="5"
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fg="0,0,255"
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bold="1" />
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<!-- #define wxSCI_V_WORD2 7 -->
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<Style name="Keywords"
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index="7"
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fg="128,0,255" />
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<!-- #define wxSCI_V_WORD3 8 -->
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<Style name="Tagname"
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index="8"
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fg="0,0,0" />
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<!-- #define wxSCI_V_USER 19 -->
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<Style name="User"
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index="19"
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fg="0,0,0" />
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<Style name="Breakpoint line"
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index="-2"
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bg="255,160,160" />
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<Style name="Debugger active line"
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index="-3"
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bg="160,160,255" />
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<Style name="Compiler error line"
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index="-4"
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bg="255,128,0" />
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<Keywords>
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<!-- Primary keywords and identifiers -->
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<Set index="0"
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value="always and assign begin xbuf buf bufif0 bufif1 case casex casez cmos
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default defparam else end endcase endfunction endmodule endprimitive endspecify
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endtable endtask event for force forever fork function if initial inout input
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integer join macromodule makefile module nand negedge nmos nor not notif0 notif1
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or output parameter pmos posedge primitive pulldown pullup rcmos real realtime reg
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repeat rnmos rpmos rtran rtranif0 rtranif1 signed specify specparam supply supply0 supply1 table
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task time tran tranif0 tranif1 tri tri0 tri1 triand trior trireg vectored wait
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wand while wire wor xnor xor" />
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<!-- Secondary keywords and identifiers -->
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<Set index="1"
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value="" />
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<!-- System Tasks -->
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<Set index="2"
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value="$readmemb $readmemh $sreadmemb $sreadmemh $display $write $strobe $monitor $fdisplay $fwrite $fstrobe
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$fmonitor $fopen $fclose $time $stime $realtime $scale $printtimescale $timeformat $stop $finish $save
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$incsave $restart $input $log $nolog $key $nokey $scope $showscopes $showscopes $showvars $showvars
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$countdrivers $list $monitoron $monitoroff $dumpon $dumpoff $dumpfile $dumplimit $dumpflush $dumpvars
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$dumpall $reset $reset $reset $reset $reset $random $getpattern $rtoi $itor $realtobits $bitstoreal
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$setup $hold $setuphold $period $width $skew $recovery" />
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<!-- User defined tasks and identifiers -->
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<Set index="3"
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value="" />
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</Keywords>
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<SampleCode value="lexer_verilog.sample"
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breakpoint_line="8"
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debug_line="10"
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error_line="11" />
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<LanguageAttributes
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LineComment="//"
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StreamCommentStart="/*"
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StreamCommentEnd="*/"
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BoxCommentStart="/* "
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BoxCommentMid=" * "
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BoxCommentEnd=" */"
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CaseSensitive="1"
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LexerCommentStyles="1,2,3"
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LexerCharacterStyles=""
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LexerStringStyles="6,12"
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LexerPreprocessorStyles="9"/>
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</Lexer>
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</CodeBlocks_lexer_properties>
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