329 lines
12 KiB
C
329 lines
12 KiB
C
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/**********************************************************************
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* $Id$ lpc17xx_spi.h 2010-05-21
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*//**
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* @file lpc17xx_spi.h
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* @brief Contains all macro definitions and function prototypes
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* support for SPI firmware library on LPC17xx
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* @version 2.0
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* @date 21. May. 2010
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* @author NXP MCU SW Application Team
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*
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* Copyright(C) 2010, NXP Semiconductor
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* All rights reserved.
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*
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***********************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors'
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* relevant copyright in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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**********************************************************************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @defgroup SPI SPI (Serial Peripheral Interface)
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* @ingroup LPC1700CMSIS_FwLib_Drivers
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* @{
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*/
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#ifndef LPC17XX_SPI_H_
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#define LPC17XX_SPI_H_
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/* Includes ------------------------------------------------------------------- */
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#include "LPC17xx.h"
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#include "lpc_types.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* Public Macros -------------------------------------------------------------- */
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/** @defgroup SPI_Public_Macros SPI Public Macros
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* @{
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*/
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/*********************************************************************//**
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* SPI configuration parameter defines
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**********************************************************************/
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/** Clock phase control bit */
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#define SPI_CPHA_FIRST ((uint32_t)(0))
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#define SPI_CPHA_SECOND ((uint32_t)(1<<3))
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/** Clock polarity control bit */
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#define SPI_CPOL_HI ((uint32_t)(0))
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#define SPI_CPOL_LO ((uint32_t)(1<<4))
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/** SPI master mode enable */
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#define SPI_SLAVE_MODE ((uint32_t)(0))
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#define SPI_MASTER_MODE ((uint32_t)(1<<5))
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/** LSB enable bit */
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#define SPI_DATA_MSB_FIRST ((uint32_t)(0))
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#define SPI_DATA_LSB_FIRST ((uint32_t)(1<<6))
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/** SPI data bit number defines */
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#define SPI_DATABIT_16 SPI_SPCR_BITS(0) /*!< Databit number = 16 */
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#define SPI_DATABIT_8 SPI_SPCR_BITS(0x08) /*!< Databit number = 8 */
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#define SPI_DATABIT_9 SPI_SPCR_BITS(0x09) /*!< Databit number = 9 */
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#define SPI_DATABIT_10 SPI_SPCR_BITS(0x0A) /*!< Databit number = 10 */
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#define SPI_DATABIT_11 SPI_SPCR_BITS(0x0B) /*!< Databit number = 11 */
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#define SPI_DATABIT_12 SPI_SPCR_BITS(0x0C) /*!< Databit number = 12 */
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#define SPI_DATABIT_13 SPI_SPCR_BITS(0x0D) /*!< Databit number = 13 */
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#define SPI_DATABIT_14 SPI_SPCR_BITS(0x0E) /*!< Databit number = 14 */
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#define SPI_DATABIT_15 SPI_SPCR_BITS(0x0F) /*!< Databit number = 15 */
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/*********************************************************************//**
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* SPI Status Flag defines
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**********************************************************************/
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/** Slave abort */
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#define SPI_STAT_ABRT SPI_SPSR_ABRT
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/** Mode fault */
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#define SPI_STAT_MODF SPI_SPSR_MODF
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/** Read overrun */
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#define SPI_STAT_ROVR SPI_SPSR_ROVR
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/** Write collision */
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#define SPI_STAT_WCOL SPI_SPSR_WCOL
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/** SPI transfer complete flag */
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#define SPI_STAT_SPIF SPI_SPSR_SPIF
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/* SPI Status Implementation definitions */
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#define SPI_STAT_DONE (1UL<<8) /**< Done */
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#define SPI_STAT_ERROR (1UL<<9) /**< Error */
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/**
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* @}
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*/
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/* Private Macros ------------------------------------------------------------- */
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/** @defgroup SPI_Private_Macros SPI Private Macros
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* @{
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*/
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/* --------------------- BIT DEFINITIONS -------------------------------------- */
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/*********************************************************************//**
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* Macro defines for SPI Control Register
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**********************************************************************/
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/** Bit enable, the SPI controller sends and receives the number
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* of bits selected by bits 11:8 */
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#define SPI_SPCR_BIT_EN ((uint32_t)(1<<2))
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/** Clock phase control bit */
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#define SPI_SPCR_CPHA_SECOND ((uint32_t)(1<<3))
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/** Clock polarity control bit */
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#define SPI_SPCR_CPOL_LOW ((uint32_t)(1<<4))
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/** SPI master mode enable */
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#define SPI_SPCR_MSTR ((uint32_t)(1<<5))
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/** LSB enable bit */
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#define SPI_SPCR_LSBF ((uint32_t)(1<<6))
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/** SPI interrupt enable bit */
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#define SPI_SPCR_SPIE ((uint32_t)(1<<7))
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/** When bit 2 of this register is 1, this field controls the
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number of bits per transfer */
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#define SPI_SPCR_BITS(n) ((n==0) ? ((uint32_t)0) : ((uint32_t)((n&0x0F)<<8)))
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/** SPI Control bit mask */
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#define SPI_SPCR_BITMASK ((uint32_t)(0xFFC))
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/*********************************************************************//**
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* Macro defines for SPI Status Register
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**********************************************************************/
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/** Slave abort */
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#define SPI_SPSR_ABRT ((uint32_t)(1<<3))
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/** Mode fault */
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#define SPI_SPSR_MODF ((uint32_t)(1<<4))
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/** Read overrun */
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#define SPI_SPSR_ROVR ((uint32_t)(1<<5))
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/** Write collision */
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#define SPI_SPSR_WCOL ((uint32_t)(1<<6))
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/** SPI transfer complete flag */
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#define SPI_SPSR_SPIF ((uint32_t)(1<<7))
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/** SPI Status bit mask */
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#define SPI_SPSR_BITMASK ((uint32_t)(0xF8))
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/*********************************************************************//**
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* Macro defines for SPI Data Register
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**********************************************************************/
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/** SPI Data low bit-mask */
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#define SPI_SPDR_LO_MASK ((uint32_t)(0xFF))
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/** SPI Data high bit-mask */
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#define SPI_SPDR_HI_MASK ((uint32_t)(0xFF00))
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/** SPI Data bit-mask */
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#define SPI_SPDR_BITMASK ((uint32_t)(0xFFFF))
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/*********************************************************************//**
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* Macro defines for SPI Clock Counter Register
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**********************************************************************/
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/** SPI clock counter setting */
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#define SPI_SPCCR_COUNTER(n) ((uint32_t)(n&0xFF))
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/** SPI clock counter bit-mask */
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#define SPI_SPCCR_BITMASK ((uint32_t)(0xFF))
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/***********************************************************************
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* Macro defines for SPI Test Control Register
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**********************************************************************/
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/** SPI Test bit */
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#define SPI_SPTCR_TEST_MASK ((uint32_t)(0xFE))
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/** SPI Test register bit mask */
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#define SPI_SPTCR_BITMASK ((uint32_t)(0xFE))
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/*********************************************************************//**
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* Macro defines for SPI Test Status Register
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**********************************************************************/
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/** Slave abort */
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#define SPI_SPTSR_ABRT ((uint32_t)(1<<3))
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/** Mode fault */
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#define SPI_SPTSR_MODF ((uint32_t)(1<<4))
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/** Read overrun */
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#define SPI_SPTSR_ROVR ((uint32_t)(1<<5))
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/** Write collision */
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#define SPI_SPTSR_WCOL ((uint32_t)(1<<6))
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/** SPI transfer complete flag */
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#define SPI_SPTSR_SPIF ((uint32_t)(1<<7))
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/** SPI Status bit mask */
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#define SPI_SPTSR_MASKBIT ((uint32_t)(0xF8))
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/*********************************************************************//**
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* Macro defines for SPI Interrupt Register
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**********************************************************************/
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/** SPI interrupt flag */
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#define SPI_SPINT_INTFLAG ((uint32_t)(1<<0))
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/** SPI interrupt register bit mask */
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#define SPI_SPINT_BITMASK ((uint32_t)(0x01))
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/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
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/** Macro to determine if it is valid SPI port number */
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#define PARAM_SPIx(n) (((uint32_t *)n)==((uint32_t *)LPC_SPI))
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/** Macro check Clock phase control mode */
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#define PARAM_SPI_CPHA(n) ((n==SPI_CPHA_FIRST) || (n==SPI_CPHA_SECOND))
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/** Macro check Clock polarity control mode */
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#define PARAM_SPI_CPOL(n) ((n==SPI_CPOL_HI) || (n==SPI_CPOL_LO))
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/** Macro check master/slave mode */
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#define PARAM_SPI_MODE(n) ((n==SPI_SLAVE_MODE) || (n==SPI_MASTER_MODE))
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/** Macro check LSB/MSB mode */
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#define PARAM_SPI_DATA_ORDER(n) ((n==SPI_DATA_MSB_FIRST) || (n==SPI_DATA_LSB_FIRST))
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/** Macro check databit value */
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#define PARAM_SPI_DATABIT(n) ((n==SPI_DATABIT_16) || (n==SPI_DATABIT_8) \
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|| (n==SPI_DATABIT_9) || (n==SPI_DATABIT_10) \
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|| (n==SPI_DATABIT_11) || (n==SPI_DATABIT_12) \
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|| (n==SPI_DATABIT_13) || (n==SPI_DATABIT_14) \
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|| (n==SPI_DATABIT_15))
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/** Macro check status flag */
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#define PARAM_SPI_STAT(n) ((n==SPI_STAT_ABRT) || (n==SPI_STAT_MODF) \
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|| (n==SPI_STAT_ROVR) || (n==SPI_STAT_WCOL) \
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|| (n==SPI_STAT_SPIF))
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/**
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* @}
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*/
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/* Public Types --------------------------------------------------------------- */
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/** @defgroup SPI_Public_Types SPI Public Types
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* @{
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*/
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/** @brief SPI configuration structure */
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typedef struct {
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uint32_t Databit; /** Databit number, should be SPI_DATABIT_x,
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where x is in range from 8 - 16 */
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uint32_t CPHA; /** Clock phase, should be:
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- SPI_CPHA_FIRST: first clock edge
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- SPI_CPHA_SECOND: second clock edge */
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uint32_t CPOL; /** Clock polarity, should be:
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- SPI_CPOL_HI: high level
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- SPI_CPOL_LO: low level */
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uint32_t Mode; /** SPI mode, should be:
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- SPI_MASTER_MODE: Master mode
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- SPI_SLAVE_MODE: Slave mode */
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uint32_t DataOrder; /** Data order, should be:
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- SPI_DATA_MSB_FIRST: MSB first
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- SPI_DATA_LSB_FIRST: LSB first */
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uint32_t ClockRate; /** Clock rate,in Hz, should not exceed
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(SPI peripheral clock)/8 */
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} SPI_CFG_Type;
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/**
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* @brief SPI Transfer Type definitions
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*/
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typedef enum {
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SPI_TRANSFER_POLLING = 0, /**< Polling transfer */
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SPI_TRANSFER_INTERRUPT /**< Interrupt transfer */
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} SPI_TRANSFER_Type;
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/**
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* @brief SPI Data configuration structure definitions
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*/
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typedef struct {
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void *tx_data; /**< Pointer to transmit data */
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void *rx_data; /**< Pointer to transmit data */
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uint32_t length; /**< Length of transfer data */
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uint32_t counter; /**< Data counter index */
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uint32_t status; /**< Current status of SPI activity */
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} SPI_DATA_SETUP_Type;
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/**
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* @}
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*/
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/* Public Functions ----------------------------------------------------------- */
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/** @defgroup SPI_Public_Functions SPI Public Functions
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* @{
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*/
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/* SPI Init/DeInit functions ---------*/
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void SPI_Init(LPC_SPI_TypeDef *SPIx, SPI_CFG_Type *SPI_ConfigStruct);
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void SPI_DeInit(LPC_SPI_TypeDef *SPIx);
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void SPI_SetClock (LPC_SPI_TypeDef *SPIx, uint32_t target_clock);
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void SPI_ConfigStructInit(SPI_CFG_Type *SPI_InitStruct);
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/* SPI transfer functions ------------*/
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void SPI_SendData(LPC_SPI_TypeDef *SPIx, uint16_t Data);
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uint16_t SPI_ReceiveData(LPC_SPI_TypeDef *SPIx);
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int32_t SPI_ReadWrite (LPC_SPI_TypeDef *SPIx, SPI_DATA_SETUP_Type *dataCfg, SPI_TRANSFER_Type xfType);
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/* SPI Interrupt functions ---------*/
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void SPI_IntCmd(LPC_SPI_TypeDef *SPIx, FunctionalState NewState);
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IntStatus SPI_GetIntStatus (LPC_SPI_TypeDef *SPIx);
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void SPI_ClearIntPending(LPC_SPI_TypeDef *SPIx);
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/* SPI get information functions-----*/
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uint8_t SPI_GetDataSize (LPC_SPI_TypeDef *SPIx);
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uint32_t SPI_GetStatus(LPC_SPI_TypeDef *SPIx);
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FlagStatus SPI_CheckStatus (uint32_t inputSPIStatus, uint8_t SPIStatus);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* LPC17XX_SPI_H_ */
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/**
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* @}
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*/
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/* --------------------------------- End Of File ------------------------------ */
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