276 lines
9.2 KiB
C++
276 lines
9.2 KiB
C++
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/*
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Copyright (c) 2011 Arduino. All right reserved.
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "pins_arduino.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Digital PinName array
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const PinName digitalPin[] = {
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PA_0, // Digital pin 0
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PA_1, // Digital pin 1
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PA_2, // Digital pin 2
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PA_3, // Digital pin 3
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PA_4, // Digital pin 4
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PA_5, // Digital pin 5
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PA_6, // Digital pin 6
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PA_7, // Digital pin 7
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PA_8, // Digital pin 8
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PA_9, // Digital pin 9
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PA_10, // Digital pin 10
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PA_11, // Digital pin 11
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PA_12, // Digital pin 12
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PA_13, // Digital pin 13
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PA_14, // Digital pin 14
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PA_15, // Digital pin 15
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PB_0, // Digital pin 16
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PB_1, // Digital pin 17
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PB_2, // Digital pin 18
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PB_3, // Digital pin 19
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PB_4, // Digital pin 20
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PB_5, // Digital pin 21
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PB_6, // Digital pin 22
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PB_7, // Digital pin 23
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PB_8, // Digital pin 24
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PB_9, // Digital pin 25
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PB_10, // Digital pin 26
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PB_11, // Digital pin 27
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PB_12, // Digital pin 28
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PB_13, // Digital pin 29
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PB_14, // Digital pin 30
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PB_15, // Digital pin 31
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PC_0, // Digital pin 32
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PC_1, // Digital pin 33
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PC_2, // Digital pin 34
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PC_3, // Digital pin 35
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PC_4, // Digital pin 36
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PC_5, // Digital pin 37
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PC_6, // Digital pin 38
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PC_7, // Digital pin 39
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PC_8, // Digital pin 40
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PC_9, // Digital pin 41
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PC_10, // Digital pin 42
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PC_11, // Digital pin 43
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PC_12, // Digital pin 44
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PC_13, // Digital pin 45
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PC_14, // Digital pin 46
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PC_15, // Digital pin 47
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PD_0, // Digital pin 48
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PD_1, // Digital pin 49
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PD_2, // Digital pin 50
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PD_3, // Digital pin 51
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PD_4, // Digital pin 52
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PD_5, // Digital pin 53
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PD_6, // Digital pin 54
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PD_7, // Digital pin 55
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PD_8, // Digital pin 56
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PD_9, // Digital pin 57
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PD_10, // Digital pin 58
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PD_11, // Digital pin 59
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PD_12, // Digital pin 60
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PD_13, // Digital pin 61
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PD_14, // Digital pin 62
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PD_15, // Digital pin 63
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PE_0, // Digital pin 64
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PE_1, // Digital pin 65
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PE_2, // Digital pin 66
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PE_3, // Digital pin 67
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PE_4, // Digital pin 68
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PE_5, // Digital pin 69
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PE_6, // Digital pin 70
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PE_7, // Digital pin 71
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PE_8, // Digital pin 72
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PE_9, // Digital pin 73
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PE_10, // Digital pin 74
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PE_11, // Digital pin 75
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PE_12, // Digital pin 76
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PE_13, // Digital pin 77
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PE_14, // Digital pin 78
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PE_15, // Digital pin 79
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PH_0, // Digital pin 80, used by the external oscillator
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PH_1 // Digital pin 81, used by the external oscillator
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};
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// Analog (Ax) pin number array
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const uint32_t analogInputPin[] = {
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0, // A0, PA0
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1, // A1, PA1
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2, // A2, PA2
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3, // A3, PA3
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4, // A4, PA4
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5, // A5, PA5
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6, // A6, PA6
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7, // A7, PA7
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16, // A8, PB0
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17, // A9, PB1
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32, // A10, PC0
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33, // A11, PC1
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34, // A12, PC2
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35, // A13, PC3
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36, // A14, PC4
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37 // A15, PC5
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};
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#ifdef __cplusplus
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}
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#endif
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// ----------------------------------------------------------------------------
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* @brief Configures the System clock source, PLL Multiplier and Divider factors,
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* AHB/APBx prescalers and Flash settings
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* @note This function should be called only once the RCC clock configuration
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* is reset to the default reset state (done in SystemInit() function).
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* @param None
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* @retval None
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*/
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/******************************************************************************/
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/* PLL (clocked by HSE) used as System clock source */
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/******************************************************************************/
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static uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct;
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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/* The voltage scaling allows optimizing the power consumption when the device is
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clocked below the maximum system frequency, to update the voltage scaling value
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regarding system frequency refer to product datasheet. */
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__HAL_RCC_PWR_CLK_ENABLE();
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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// Enable HSE oscillator and activate PLL with HSE as source
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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if (bypass == 0) {
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RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
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} else {
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RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
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}
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 1000000L; // Expects an 8 MHz external clock by default. Redefine HSE_VALUE if not
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RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 168 MHz (336 MHz / 2)
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RCC_OscInitStruct.PLL.PLLQ = 7;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
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return 0; // FAIL
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}
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/* Output clock on MCO1 pin(PA8) for debugging purpose */
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/*
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if (bypass == 0)
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HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
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else
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HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
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*/
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return 1; // OK
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}
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/******************************************************************************/
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/* PLL (clocked by HSI) used as System clock source */
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/******************************************************************************/
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uint8_t SetSysClock_PLL_HSI(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct;
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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/* The voltage scaling allows optimizing the power consumption when the device is
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clocked below the maximum system frequency, to update the voltage scaling value
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regarding system frequency refer to product datasheet. */
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__HAL_RCC_PWR_CLK_ENABLE();
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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// Enable HSI oscillator and activate PLL with HSI as source
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
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RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 168 MHz (336 MHz / 2)
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RCC_OscInitStruct.PLL.PLLQ = 7;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
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return 0; // FAIL
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}
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/* Output clock on MCO1 pin(PA8) for debugging purpose */
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//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
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return 1; // OK
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}
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WEAK void SystemClock_Config(void)
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{
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/* 1- If fail try to start with HSE and external xtal */
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if (SetSysClock_PLL_HSE(0) == 0) {
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/* 2- Try to start with HSE and external clock */
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if (SetSysClock_PLL_HSE(1) == 0) {
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/* 3- If fail start with HSI clock */
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if (SetSysClock_PLL_HSI() == 0) {
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Error_Handler();
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}
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}
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}
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/* Ensure CCM RAM clock is enabled */
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__HAL_RCC_CCMDATARAMEN_CLK_ENABLE();
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/* Output clock on MCO2 pin(PC9) for debugging purpose */
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//HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
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}
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#ifdef __cplusplus
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}
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#endif
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