Add memory barrier, optimal interrupt on-off
Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)
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@ -46,6 +46,11 @@ static void TXBegin(void) {
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// Disable UART interrupt in NVIC
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NVIC_DisableIRQ( UART_IRQn );
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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// Disable clock
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pmc_disable_periph_clk( ID_UART );
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@ -99,6 +99,11 @@ void HAL_timer_start(const uint8_t timer_num, const uint32_t frequency) {
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// Disable interrupt, just in case it was already enabled
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NVIC_DisableIRQ(irq);
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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// Disable timer interrupt
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tc->TC_CHANNEL[channel].TC_IDR = TC_IDR_CPCS;
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@ -133,6 +138,11 @@ void HAL_timer_enable_interrupt(const uint8_t timer_num) {
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void HAL_timer_disable_interrupt(const uint8_t timer_num) {
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IRQn_Type irq = TimerConfig[timer_num].IRQ_Id;
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NVIC_DisableIRQ(irq);
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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}
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// missing from CMSIS: Check if interrupt is enabled or not
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@ -245,6 +245,11 @@
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// Disable UART interrupt in NVIC
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NVIC_DisableIRQ( HWUART_IRQ );
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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// Disable clock
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pmc_disable_periph_clk( HWUART_IRQ_ID );
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@ -290,6 +295,11 @@
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// Disable UART interrupt in NVIC
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NVIC_DisableIRQ( HWUART_IRQ );
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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pmc_disable_periph_clk( HWUART_IRQ_ID );
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}
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@ -68,6 +68,11 @@ void watchdogSetup(void) {
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// Disable WDT interrupt (just in case, to avoid triggering it!)
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NVIC_DisableIRQ(WDT_IRQn);
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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// Initialize WDT with the given parameters
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WDT_Enable(WDT, value);
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@ -143,6 +143,11 @@ FORCE_INLINE static void HAL_timer_disable_interrupt(const uint8_t timer_num) {
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case 0: NVIC_DisableIRQ(TIMER0_IRQn); // Disable interrupt handler
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case 1: NVIC_DisableIRQ(TIMER1_IRQn); // Disable interrupt handler
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}
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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}
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// This function is missing from CMSIS
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@ -258,6 +258,11 @@ bool LPC1768_PWM_attach_pin(pin_t pin, uint32_t min /* = 1 */, uint32_t max /* =
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// OK to update the active table because the
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// ISR doesn't use any of the changed items
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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if (ISR_table_update) //use work table if that's the newest
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temp_table = work_table;
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else
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@ -342,6 +347,11 @@ bool LPC1768_PWM_detach_pin(pin_t pin) {
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//// interrupt controlled PWM code
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NVIC_DisableIRQ(HAL_PWM_TIMER_IRQn);
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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if (ISR_table_update) {
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ISR_table_update = false; // don't update yet - have another update to do
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NVIC_EnableIRQ(HAL_PWM_TIMER_IRQn); // re-enable PWM interrupts
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@ -428,6 +438,12 @@ bool LPC1768_PWM_write(pin_t pin, uint32_t value) {
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//// interrupt controlled PWM code
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NVIC_DisableIRQ(HAL_PWM_TIMER_IRQn);
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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if (!ISR_table_update) // use the most up to date table
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COPY_ACTIVE_TABLE; // copy active table into work table
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@ -456,6 +472,11 @@ bool useable_hardware_PWM(pin_t pin) {
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NVIC_DisableIRQ(HAL_PWM_TIMER_IRQn);
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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bool return_flag = false;
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for (uint8_t i = 0; i < NUM_ISR_PWMS; i++) // see if it's already setup
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if (active_table[i].pin == pin) return_flag = true;
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@ -123,6 +123,11 @@ void HAL_timer_enable_interrupt(const uint8_t timer_num) {
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void HAL_timer_disable_interrupt(const uint8_t timer_num) {
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HAL_NVIC_DisableIRQ(timerConfig[timer_num].IRQ_Id);
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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}
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hal_timer_t HAL_timer_get_compare(const uint8_t timer_num) {
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@ -127,6 +127,11 @@ void HAL_timer_enable_interrupt(const uint8_t timer_num) {
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void HAL_timer_disable_interrupt(const uint8_t timer_num) {
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HAL_NVIC_DisableIRQ(timerConfig[timer_num].IRQ_Id);
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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}
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hal_timer_t HAL_timer_get_compare(const uint8_t timer_num) {
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@ -29,6 +29,22 @@
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#include "HAL.h"
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#include "HAL_timers_Teensy.h"
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/** \brief Instruction Synchronization Barrier
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Instruction Synchronization Barrier flushes the pipeline in the processor,
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so that all instructions following the ISB are fetched from cache or
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memory, after the instruction has been completed.
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*/
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FORCE_INLINE static void __ISB(void) {
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__asm__ __volatile__("isb 0xF":::"memory");
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}
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/** \brief Data Synchronization Barrier
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This function acts as a special kind of Data Memory Barrier.
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It completes when all explicit memory accesses before this instruction complete.
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*/
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FORCE_INLINE static void __DSB(void) {
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__asm__ __volatile__("dsb 0xF":::"memory");
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}
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void HAL_timer_start(const uint8_t timer_num, const uint32_t frequency) {
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switch (timer_num) {
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@ -65,6 +81,11 @@ void HAL_timer_disable_interrupt(const uint8_t timer_num) {
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case 0: NVIC_DISABLE_IRQ(IRQ_FTM0); break;
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case 1: NVIC_DISABLE_IRQ(IRQ_FTM1); break;
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}
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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}
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bool HAL_timer_interrupt_enabled(const uint8_t timer_num) {
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@ -73,7 +73,6 @@ static uint8_t LEDs[8] = { 0 };
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#endif
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void Max7219_PutByte(uint8_t data) {
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CRITICAL_SECTION_START;
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for (uint8_t i = 8; i--;) {
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SIG_DELAY();
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WRITE(MAX7219_CLK_PIN, LOW); // tick
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SIG_DELAY();
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data <<= 1;
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}
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CRITICAL_SECTION_END;
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}
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void Max7219(const uint8_t reg, const uint8_t data) {
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SIG_DELAY();
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CRITICAL_SECTION_START;
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WRITE(MAX7219_LOAD_PIN, LOW); // begin
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SIG_DELAY();
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Max7219_PutByte(reg); // specify register
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WRITE(MAX7219_LOAD_PIN, LOW); // and tell the chip to load the data
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SIG_DELAY();
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WRITE(MAX7219_LOAD_PIN, HIGH);
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CRITICAL_SECTION_END;
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SIG_DELAY();
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}
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@ -1085,9 +1085,7 @@ void Temperature::updateTemperaturesFromRawValues() {
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watchdog_reset();
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#endif
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CRITICAL_SECTION_START;
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temp_meas_ready = false;
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CRITICAL_SECTION_END;
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}
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