🐛 Fix AVR DELAY_US int overflow (#22268)
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@ -97,43 +97,65 @@ void calibrate_delay_loop();
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#define DELAY_US(x) DelayCycleFnc((x) * ((F_CPU) / 1000000UL))
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#elif defined(__AVR__)
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#define nop() __asm__ __volatile__("nop;\n\t":::)
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FORCE_INLINE static void __delay_4cycles(uint8_t cy) {
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__asm__ __volatile__(
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L("1")
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A("dec %[cnt]")
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A("nop")
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A("brne 1b")
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: [cnt] "+r"(cy) // output: +r means input+output
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: // input:
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: "cc" // clobbers:
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);
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FORCE_INLINE static void __delay_up_to_3c(uint8_t cycles) {
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switch (cycles) {
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case 3:
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__asm__ __volatile__(A("RJMP .+0") A("NOP"));
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break;
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case 2:
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__asm__ __volatile__(A("RJMP .+0"));
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break;
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case 1:
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__asm__ __volatile__(A("NOP"));
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break;
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}
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}
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// Delay in cycles
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FORCE_INLINE static void DELAY_CYCLES(uint16_t x) {
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if (__builtin_constant_p(x)) {
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#define MAXNOPS 4
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if (x <= (MAXNOPS)) {
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switch (x) { case 4: nop(); case 3: nop(); case 2: nop(); case 1: nop(); }
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FORCE_INLINE static void DELAY_CYCLES(uint16_t cycles) {
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if (__builtin_constant_p(cycles)) {
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if (cycles <= 3) {
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__delay_up_to_3c(cycles);
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}
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else if (cycles == 4) {
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__delay_up_to_3c(2);
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__delay_up_to_3c(2);
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}
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else {
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const uint32_t rem = (x) % (MAXNOPS);
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switch (rem) { case 3: nop(); case 2: nop(); case 1: nop(); }
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if ((x = (x) / (MAXNOPS)))
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__delay_4cycles(x); // if need more then 4 nop loop is more optimal
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}
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cycles -= 1 + 4; // Compensate for the first LDI (1) and the first round (4)
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__delay_up_to_3c(cycles % 4);
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#undef MAXNOPS
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cycles /= 4;
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// The following code burns [1 + 4 * (rounds+1)] cycles
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uint16_t dummy;
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__asm__ __volatile__(
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// "manually" load counter from constants, otherwise the compiler may optimize this part away
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A("LDI %A[rounds], %[l]") // 1c
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A("LDI %B[rounds], %[h]") // 1c (compensating the non branching BRCC)
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L("1")
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A("SBIW %[rounds], 1") // 2c
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A("BRCC 1b") // 2c when branching, else 1c (end of loop)
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: // Outputs ...
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[rounds] "=w" (dummy) // Restrict to a wo (=) 16 bit register pair (w)
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: // Inputs ...
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[l] "M" (cycles%256), // Restrict to 0..255 constant (M)
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[h] "M" (cycles/256) // Restrict to 0..255 constant (M)
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:// Clobbers ...
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"cc" // Indicate we are modifying flags like Carry (cc)
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);
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}
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}
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else {
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__asm__ __volatile__(
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L("1")
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A("SBIW %[cycles], 4") // 2c
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A("BRCC 1b") // 2c when branching, else 1c (end of loop)
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: [cycles] "+w" (cycles) // output: Restrict to a rw (+) 16 bit register pair (w)
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: // input: -
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: "cc" // clobbers: We are modifying flags like Carry (cc)
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);
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}
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else if ((x >>= 2))
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__delay_4cycles(x);
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}
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#undef nop
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// Delay in microseconds
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#define DELAY_US(x) DELAY_CYCLES((x) * ((F_CPU) / 1000000UL))
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