Commit graph

341 commits

Author SHA1 Message Date
etagle e7e896e7d7 More tweaks to fastio_Due.h 2018-07-04 17:57:47 -05:00
Chris Pepper 55f4744e54 [LPC176x] Endstop Interrupts Feature (#11202)
Enable the endstop interrupts feature for LPC176x boards. Although Smoothieboard chose to use non-interrupt capable pins for their endstops, and this has been copied by clones, so they can't use it.
2018-07-04 17:51:45 -05:00
Chris Pepper 5abf5bc8a7 [LPC176x] Fix Interrupt forward declarations (#11200) 2018-07-04 17:43:14 -05:00
Chris Pepper 5616581eb1 [LPC176x] Update fastio _GET_INPUT, _GET_OUTPUT macros (#11168) 2018-07-01 23:02:38 -05:00
Scott Lahteine 8a8eae8d97
Implement more fastio_Due macros (#11165) 2018-07-01 01:24:06 -05:00
Scott Lahteine fc10101b06 Tweaks to fastio_Due.h 2018-06-30 00:15:50 -05:00
Alexander Amelkin ffdbc1f42c STM32F1: Fix SD card persistent store API (#11090) 2018-06-26 14:41:23 -04:00
Scott Lahteine d86f25ab63 Fix Serial ISR priority for LPC1768
Co-Authored-By: p3p <p3p@p3psoft.co.uk>
2018-06-25 12:15:41 -04:00
Scott Lahteine 99591dc20c
Filter endstops state at all times (#11066) 2018-06-21 20:14:16 -05:00
Chris Pepper 0312c42f9d [2.0.x] LPC176x Serial cleanup (#11032) 2018-06-16 20:59:22 -05:00
Scott Lahteine c1269c2ec1 Tweak AVR critical section defines 2018-06-16 17:42:32 -05:00
Chris Pepper f88adcbfd5 [2.0.x][LPC176x] Fix binary linking broken by pio update (#11026) 2018-06-15 15:32:51 -05:00
Simon Jouet e2aeda61ed HAL for Espressif ESP32 Wifi 2018-06-13 19:33:35 -05:00
Scott Lahteine 19d4c7c1cd Tweak HAL header comments 2018-06-13 19:08:42 -05:00
etagle a215725df6 Fix stepper pulse timing
Always honor minimum period on stepper pulse generation, and fix timing calculations

Signed-off-by: etagle <ejtagle@hotmail.com>
2018-06-12 21:34:24 -05:00
Scott Lahteine a9861a780e Tweak HAL heading 2018-06-12 19:40:17 -05:00
Scott Lahteine cf53e502a2 No need to set input after attachInterrupt 2018-06-12 18:43:11 -05:00
Karl Andersson e0276d2f32 Official STMicroelectronics Arduino Core STM32F4 HAL compatibility (#11006) 2018-06-12 18:38:00 -05:00
Scott Lahteine 4dbec774b5 HAL_*_TIMER_RATE => *_TIMER_RATE 2018-06-12 16:39:12 -05:00
Scott Lahteine 9b945c13a1 Fix STM32F1 ISR_ENABLED 2018-06-11 22:09:45 -05:00
Alexey Shvetsov 2ddba201c0 STM32F1 HAL Fixes (#10999)
- Enable / disable interrupts with `__iSeiRetVal` / `__iCliRetVal`
- Add STM32F1 to Travis CI tests
2018-06-11 20:00:56 -05:00
Eduardo José Tagle 5590c8ffd0 Fix MarlinSerial (AVR) (#10991)
An undocumented hw bug makes the UART lose chars when RX ISR is disabled, even for a very small amount of time. This happens when RX_BUFFER > 256, and the result is corrupted received commands. Solved by implementing pseudo-atomic operations on 16bit indices.
2018-06-10 20:32:20 -05:00
Scott Lahteine 117fd007a9 Followup to pin error change 2018-06-10 19:28:45 -05:00
etagle 99af086cea Add hidden Serial overflow debug options 2018-06-10 04:25:42 -05:00
etagle d90e8fcad9 Fix XON/XOFF implementation
Pointed out by @GMagician
2018-06-10 04:25:42 -05:00
Scott Lahteine 3701869e6c Add HAL_timer_start for AVR, use stepper timer to time pulses 2018-06-09 22:30:13 -05:00
Scott Lahteine a426986df8
Ensure pins set to INPUT after attachInterrupt (#10928) 2018-06-06 20:59:08 -05:00
Giuliano c9d1a620d4 [2.0.x] fix indentations (#10934) 2018-06-05 02:03:26 -05:00
Scott Lahteine c685c7b7dd STM32F4: All pins can do PWM 2018-06-03 04:30:15 -05:00
Eduardo José Tagle d3c02410a8 [2.0.x] Small assorted collection of fixes and improvements (#10911)
* Misc fixes and improvements

- Get rid of most critical sections on the Serial port drivers for AVR and DUE. Proper usage of FIFOs should allow interrupts to stay enabled without harm to queuing and dequeuing.
  Also, with 8-bit indices (for AVR) and up to 32-bit indices (for ARM), there is no need to protect reads and writes to those indices.
- Simplify the XON/XOFF logic quite a bit. Much cleaner now (both for AVR and ARM)
- Prevent a race condition (edge case) that could happen when estimating the proper value for the stepper timer (by reading it) and writing the calculated value for the time to the next ISR by disabling interrupts in those critical and small sections of the code - The problem could lead to lost steps.
- Fix dual endstops not properly homing bug (maybe).

* Set position immediately when possible
2018-06-01 19:02:22 -05:00
Chris Pepper d87257f63c [2.0.x][LPC176x] Fix PIO build flags (#10909)
Don't build and link with different flags, the binary may not work.
2018-05-31 19:08:31 -05:00
Scott Lahteine cbcb284f4a Allow libServo::attach to work on Teensy 3.5/3.6 2018-05-28 20:56:24 -05:00
Chris Pepper f89f7c4a82 [2.0.x][LPC176x][Build] Force single precision constants, disable freestanding (#10892) 2018-05-28 19:38:22 -05:00
android444 16da5c62d0 Teensy 3.x fastio pullup (#10890) 2018-05-28 16:25:12 -05:00
Scott Lahteine 9b9b62b218 delay(SERVO_DELAY) => safe_delay(servo_delay[servo_index]) 2018-05-28 03:44:32 -05:00
android444 9c235ef821 [HAL]Add support for ST7920 - Teensy 3.x (#10872) 2018-05-27 03:36:57 -05:00
Bob-the-Kuhn 1c0ad8bbae wrong type of exit method 2018-05-26 08:17:03 -05:00
Eduardo José Tagle 6f330f397e [2.0.x] Buffer overflow and scroll fix, UTF8 cleanup (#10844) 2018-05-25 23:32:37 -05:00
Bob Kuhn 235facd545 install AVRDUDE 5.10, faster disk find for LPC1768 (#10849) 2018-05-25 20:26:48 -05:00
Bob Kuhn e2db509d58 [2.0.x] Update/Fix LPC1768 extra script upload_extra_script.py (#10843)
* Use a different method to find the volume info in Windows
2018-05-25 04:31:18 -05:00
Scott Lahteine 5f8591528e Remove #pragmas that don't help c files 2018-05-23 23:47:16 -05:00
Scott Lahteine c89649b46e Suppress U8glib build warnings 2018-05-23 02:47:36 -05:00
Scott Lahteine 4118199ddd Tweaks to core headers 2018-05-21 20:32:18 -05:00
Bob Kuhn 6dfbb39f83 [LPC1768] Add error-handling to upload script, update autobuild.py (#10802) 2018-05-20 21:22:04 -05:00
etagle 569df3fc0c Fix interrupt-based endstop detection
- Also implemented real endstop reading on interrupt.
2018-05-20 07:10:24 -05:00
etagle 0566badcef Add memory barrier, optimal interrupt on-off
Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)
2018-05-20 02:39:34 -05:00
Scott Lahteine c2fb2f54a1 Use assembly for AVR ISR vectors
Co-Authored-By: ejtagle <ejtagle@hotmail.com>
2018-05-20 01:58:51 -05:00
Scott Lahteine 206014a957 Fix LPC176x timer functions
Co-Authored-By: ejtagle <ejtagle@hotmail.com>
2018-05-20 01:58:51 -05:00
Scott Lahteine 59f7861bcb
Move backtrace to the HAL folder (#10790) 2018-05-20 01:33:21 -05:00
Scott Lahteine c173a31060 Fix some compile warnings 2018-05-19 16:54:48 -05:00