etagle 0566badcef Add memory barrier, optimal interrupt on-off ... Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)		2018-05-20 02:39:34 -05:00
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config	Add FAN_MAX_PWM to example configs	2018-05-15 21:18:47 -05:00
core	Improve NOMORE, NOLESS, and LIMIT macros	2018-05-17 18:23:14 -05:00
feature	Add memory barrier, optimal interrupt on-off	2018-05-20 02:39:34 -05:00
gcode	Add HAS_HOTEND_OFFSET_Z conditional	2018-05-19 17:05:15 -05:00
HAL	Add memory barrier, optimal interrupt on-off	2018-05-20 02:39:34 -05:00
inc	Add HAS_HOTEND_OFFSET_Z conditional	2018-05-19 17:05:15 -05:00
lcd	Tweak some LCD comments	2018-05-19 21:00:08 -05:00
libs	Smarter MIN, MAX, ABS macros	2018-05-13 04:52:56 -05:00
module	Add memory barrier, optimal interrupt on-off	2018-05-20 02:39:34 -05:00
pins	add AT90USB support & add items to popup menu (#10779)	2018-05-19 17:39:26 -05:00
sd	Move Stepper::synchronize to Planner (#10713)	2018-05-12 01:38:02 -05:00
Marlin.cpp	Fix switching extruder	2018-05-19 17:05:15 -05:00
Marlin.h	Apply _AXIS macro	2018-05-13 06:51:01 -05:00