909 lines
34 KiB
C++
909 lines
34 KiB
C++
/**
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* Marlin 3D Printer Firmware
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* Copyright (C) 2016 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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*
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* Based on Sprinter and grbl.
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* Copyright (C) 2011 Camiel Gubbels / Erik van der Zalm
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/**
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* Software SPI functions originally from Arduino Sd2Card Library
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* Copyright (C) 2009 by William Greiman
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*
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* Completely rewritten and tuned by Eduardo José Tagle in 2017/2018
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* in ARM thumb2 inline assembler and tuned for maximum speed and performance
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* allowing SPI clocks of up to 12 Mhz to increase SD card read/write performance
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*/
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/**
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* Description: HAL for Arduino Due and compatible (SAM3X8E)
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*
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* For ARDUINO_ARCH_SAM
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*/
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#ifdef ARDUINO_ARCH_SAM
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// --------------------------------------------------------------------------
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// Includes
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// --------------------------------------------------------------------------
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#include "../../inc/MarlinConfig.h"
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// --------------------------------------------------------------------------
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// Public Variables
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// --------------------------------------------------------------------------
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// --------------------------------------------------------------------------
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// Public functions
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// --------------------------------------------------------------------------
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#if ENABLED(DUE_SOFTWARE_SPI)
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// --------------------------------------------------------------------------
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// software SPI
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// --------------------------------------------------------------------------
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// set optimization so ARDUINO optimizes this file
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#pragma GCC optimize (3)
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/* ---------------- Delay Cycles routine -------------- */
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/* https://blueprints.launchpad.net/gcc-arm-embedded/+spec/delay-cycles */
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#define nop() __asm__ __volatile__("nop;\n\t":::)
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FORCE_INLINE static void __delay_4cycles(uint32_t cy) { // +1 cycle
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#if ARCH_PIPELINE_RELOAD_CYCLES<2
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#define EXTRA_NOP_CYCLES "nop"
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#else
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#define EXTRA_NOP_CYCLES ""
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#endif
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__asm__ __volatile__(
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".syntax unified" "\n\t" // is to prevent CM0,CM1 non-unified syntax
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L("loop%=")
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A("subs %[cnt],#1")
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A(EXTRA_NOP_CYCLES)
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A("bne loop%=")
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: [cnt]"+r"(cy) // output: +r means input+output
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: // input:
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: "cc" // clobbers:
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);
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}
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FORCE_INLINE static void DELAY_CYCLES(uint32_t x) {
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if (__builtin_constant_p(x)) {
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#define MAXNOPS 4
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if (x <= (MAXNOPS)) {
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switch (x) { case 4: nop(); case 3: nop(); case 2: nop(); case 1: nop(); }
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}
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else { // because of +1 cycle inside delay_4cycles
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const uint32_t rem = (x - 1) % (MAXNOPS);
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switch (rem) { case 3: nop(); case 2: nop(); case 1: nop(); }
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if ((x = (x - 1) / (MAXNOPS)))
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__delay_4cycles(x); // if need more then 4 nop loop is more optimal
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}
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}
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else
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__delay_4cycles(x / 4);
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}
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/* ---------------- Delay in nanoseconds and in microseconds */
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#define DELAY_NS(x) DELAY_CYCLES( (x) * (F_CPU/1000000) / 1000)
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typedef uint8_t (*pfnSpiTransfer) (uint8_t b);
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typedef void (*pfnSpiRxBlock)(uint8_t* buf, uint32_t nbyte);
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typedef void (*pfnSpiTxBlock)(const uint8_t* buf, uint32_t nbyte);
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/* ---------------- Macros to be able to access definitions from asm */
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#define _PORT(IO) DIO ## IO ## _WPORT
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#define _PIN_MASK(IO) MASK(DIO ## IO ## _PIN)
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#define _PIN_SHIFT(IO) DIO ## IO ## _PIN
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#define PORT(IO) _PORT(IO)
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#define PIN_MASK(IO) _PIN_MASK(IO)
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#define PIN_SHIFT(IO) _PIN_SHIFT(IO)
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// run at ~8 .. ~10Mhz - Tx version (Rx data discarded)
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static uint8_t spiTransferTx0(uint8_t bout) { // using Mode 0
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register uint32_t MOSI_PORT_PLUS30 = ((uint32_t) PORT(MOSI_PIN)) + 0x30; /* SODR of port */
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register uint32_t MOSI_MASK = PIN_MASK(MOSI_PIN);
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register uint32_t SCK_PORT_PLUS30 = ((uint32_t) PORT(SCK_PIN)) + 0x30; /* SODR of port */
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register uint32_t SCK_MASK = PIN_MASK(SCK_PIN);
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register uint32_t idx = 0;
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/* Negate bout, as the assembler requires a negated value */
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bout = ~bout;
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/* The software SPI routine */
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__asm__ __volatile__(
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".syntax unified" "\n\t" // is to prevent CM0,CM1 non-unified syntax
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/* Bit 7 */
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A("ubfx %[idx],%[txval],#7,#1") /* Place bit 7 in bit 0 of idx*/
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A("str %[mosi_mask],[%[mosi_port], %[idx],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[idx],%[txval],#6,#1") /* Place bit 6 in bit 0 of idx*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 6 */
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A("str %[mosi_mask],[%[mosi_port], %[idx],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[idx],%[txval],#5,#1") /* Place bit 5 in bit 0 of idx*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 5 */
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A("str %[mosi_mask],[%[mosi_port], %[idx],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[idx],%[txval],#4,#1") /* Place bit 4 in bit 0 of idx*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 4 */
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A("str %[mosi_mask],[%[mosi_port], %[idx],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[idx],%[txval],#3,#1") /* Place bit 3 in bit 0 of idx*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 3 */
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A("str %[mosi_mask],[%[mosi_port], %[idx],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[idx],%[txval],#2,#1") /* Place bit 2 in bit 0 of idx*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 2 */
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A("str %[mosi_mask],[%[mosi_port], %[idx],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[idx],%[txval],#1,#1") /* Place bit 1 in bit 0 of idx*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 1 */
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A("str %[mosi_mask],[%[mosi_port], %[idx],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[idx],%[txval],#0,#1") /* Place bit 0 in bit 0 of idx*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 0 */
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A("str %[mosi_mask],[%[mosi_port], %[idx],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("nop") /* Result will be 0 */
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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: [idx]"+r"( idx )
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: [txval]"r"( bout ) ,
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[mosi_mask]"r"( MOSI_MASK ),
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[mosi_port]"r"( MOSI_PORT_PLUS30 ),
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[sck_mask]"r"( SCK_MASK ),
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[sck_port]"r"( SCK_PORT_PLUS30 )
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: "cc"
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);
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return 0;
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}
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// Calculates the bit band alias address and returns a pointer address to word.
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// addr: The byte address of bitbanding bit.
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// bit: The bit position of bitbanding bit.
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#define BITBAND_ADDRESS(addr, bit) \
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(((uint32_t)(addr) & 0xF0000000) + 0x02000000 + ((uint32_t)(addr)&0xFFFFF)*32 + (bit)*4)
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// run at ~8 .. ~10Mhz - Rx version (Tx line not altered)
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static uint8_t spiTransferRx0(uint8_t bout) { // using Mode 0
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register uint32_t bin = 0;
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register uint32_t work = 0;
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register uint32_t BITBAND_MISO_PORT = BITBAND_ADDRESS( ((uint32_t)PORT(MISO_PIN))+0x3C, PIN_SHIFT(MISO_PIN)); /* PDSR of port in bitband area */
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register uint32_t SCK_PORT_PLUS30 = ((uint32_t) PORT(SCK_PIN)) + 0x30; /* SODR of port */
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register uint32_t SCK_MASK = PIN_MASK(SCK_PIN);
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UNUSED(bout);
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/* The software SPI routine */
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__asm__ __volatile__(
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".syntax unified" "\n\t" // is to prevent CM0,CM1 non-unified syntax
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/* bit 7 */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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A("bfi %[bin],%[work],#7,#1") /* Store read bit as the bit 7 */
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/* bit 6 */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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A("bfi %[bin],%[work],#6,#1") /* Store read bit as the bit 6 */
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/* bit 5 */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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A("bfi %[bin],%[work],#5,#1") /* Store read bit as the bit 5 */
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/* bit 4 */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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A("bfi %[bin],%[work],#4,#1") /* Store read bit as the bit 4 */
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/* bit 3 */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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A("bfi %[bin],%[work],#3,#1") /* Store read bit as the bit 3 */
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/* bit 2 */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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A("bfi %[bin],%[work],#2,#1") /* Store read bit as the bit 2 */
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/* bit 1 */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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A("bfi %[bin],%[work],#1,#1") /* Store read bit as the bit 1 */
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/* bit 0 */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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A("bfi %[bin],%[work],#0,#1") /* Store read bit as the bit 0 */
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: [bin]"+r"(bin),
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[work]"+r"(work)
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: [bitband_miso_port]"r"( BITBAND_MISO_PORT ),
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[sck_mask]"r"( SCK_MASK ),
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[sck_port]"r"( SCK_PORT_PLUS30 )
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: "cc"
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);
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return bin;
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}
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// run at ~4Mhz
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static uint8_t spiTransfer1(uint8_t b) { // using Mode 0
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int bits = 8;
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do {
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WRITE(MOSI_PIN, b & 0x80);
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b <<= 1; // little setup time
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WRITE(SCK_PIN, HIGH);
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DELAY_NS(125); // 10 cycles @ 84mhz
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b |= (READ(MISO_PIN) != 0);
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WRITE(SCK_PIN, LOW);
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DELAY_NS(125); // 10 cycles @ 84mhz
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} while (--bits);
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return b;
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}
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// all the others
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static uint32_t spiDelayCyclesX4 = (F_CPU/1000000); // 4uS => 125khz
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static uint8_t spiTransferX(uint8_t b) { // using Mode 0
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int bits = 8;
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do {
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WRITE(MOSI_PIN, b & 0x80);
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b <<= 1; // little setup time
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WRITE(SCK_PIN, HIGH);
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__delay_4cycles(spiDelayCyclesX4);
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b |= (READ(MISO_PIN) != 0);
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WRITE(SCK_PIN, LOW);
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__delay_4cycles(spiDelayCyclesX4);
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} while (--bits);
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return b;
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}
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// Pointers to generic functions for byte transfers
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static pfnSpiTransfer spiTransferTx = spiTransferX;
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static pfnSpiTransfer spiTransferRx = spiTransferX;
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// Block transfers run at ~8 .. ~10Mhz - Tx version (Rx data discarded)
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static void spiTxBlock0(const uint8_t* ptr, uint32_t todo) {
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register uint32_t MOSI_PORT_PLUS30 = ((uint32_t) PORT(MOSI_PIN)) + 0x30; /* SODR of port */
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register uint32_t MOSI_MASK = PIN_MASK(MOSI_PIN);
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register uint32_t SCK_PORT_PLUS30 = ((uint32_t) PORT(SCK_PIN)) + 0x30; /* SODR of port */
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register uint32_t SCK_MASK = PIN_MASK(SCK_PIN);
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register uint32_t work = 0;
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register uint32_t txval = 0;
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/* The software SPI routine */
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__asm__ __volatile__(
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".syntax unified" "\n\t" // is to prevent CM0,CM1 non-unified syntax
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L("loop%=")
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A("ldrb.w %[txval], [%[ptr]], #1") /* Load value to send, increment buffer */
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A("mvn %[txval],%[txval]") /* Negate value */
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/* Bit 7 */
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A("ubfx %[work],%[txval],#7,#1") /* Place bit 7 in bit 0 of work*/
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A("str %[mosi_mask],[%[mosi_port], %[work],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[work],%[txval],#6,#1") /* Place bit 6 in bit 0 of work*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 6 */
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A("str %[mosi_mask],[%[mosi_port], %[work],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[work],%[txval],#5,#1") /* Place bit 5 in bit 0 of work*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 5 */
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A("str %[mosi_mask],[%[mosi_port], %[work],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[work],%[txval],#4,#1") /* Place bit 4 in bit 0 of work*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 4 */
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A("str %[mosi_mask],[%[mosi_port], %[work],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[work],%[txval],#3,#1") /* Place bit 3 in bit 0 of work*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 3 */
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A("str %[mosi_mask],[%[mosi_port], %[work],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[work],%[txval],#2,#1") /* Place bit 2 in bit 0 of work*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 2 */
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A("str %[mosi_mask],[%[mosi_port], %[work],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[work],%[txval],#1,#1") /* Place bit 1 in bit 0 of work*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 1 */
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A("str %[mosi_mask],[%[mosi_port], %[work],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[work],%[txval],#0,#1") /* Place bit 0 in bit 0 of work*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 0 */
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A("str %[mosi_mask],[%[mosi_port], %[work],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
|
|
A("str %[sck_mask],[%[sck_port]]") /* SODR */
|
|
A("subs %[todo],#1") /* Decrement count of pending words to send, update status */
|
|
A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
|
|
A("bne.n loop%=") /* Repeat until done */
|
|
|
|
: [ptr]"+r" ( ptr ) ,
|
|
[todo]"+r" ( todo ) ,
|
|
[work]"+r"( work ) ,
|
|
[txval]"+r"( txval )
|
|
: [mosi_mask]"r"( MOSI_MASK ),
|
|
[mosi_port]"r"( MOSI_PORT_PLUS30 ),
|
|
[sck_mask]"r"( SCK_MASK ),
|
|
[sck_port]"r"( SCK_PORT_PLUS30 )
|
|
: "cc"
|
|
);
|
|
}
|
|
|
|
static void spiRxBlock0(uint8_t* ptr, uint32_t todo) {
|
|
register uint32_t bin = 0;
|
|
register uint32_t work = 0;
|
|
register uint32_t BITBAND_MISO_PORT = BITBAND_ADDRESS( ((uint32_t)PORT(MISO_PIN))+0x3C, PIN_SHIFT(MISO_PIN)); /* PDSR of port in bitband area */
|
|
register uint32_t SCK_PORT_PLUS30 = ((uint32_t) PORT(SCK_PIN)) + 0x30; /* SODR of port */
|
|
register uint32_t SCK_MASK = PIN_MASK(SCK_PIN);
|
|
|
|
/* The software SPI routine */
|
|
__asm__ __volatile__(
|
|
".syntax unified" "\n\t" // is to prevent CM0,CM1 non-unified syntax
|
|
|
|
L("loop%=")
|
|
|
|
/* bit 7 */
|
|
A("str %[sck_mask],[%[sck_port]]") /* SODR */
|
|
A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
|
|
A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
|
|
A("bfi %[bin],%[work],#7,#1") /* Store read bit as the bit 7 */
|
|
|
|
/* bit 6 */
|
|
A("str %[sck_mask],[%[sck_port]]") /* SODR */
|
|
A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
|
|
A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
|
|
A("bfi %[bin],%[work],#6,#1") /* Store read bit as the bit 6 */
|
|
|
|
/* bit 5 */
|
|
A("str %[sck_mask],[%[sck_port]]") /* SODR */
|
|
A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
|
|
A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
|
|
A("bfi %[bin],%[work],#5,#1") /* Store read bit as the bit 5 */
|
|
|
|
/* bit 4 */
|
|
A("str %[sck_mask],[%[sck_port]]") /* SODR */
|
|
A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
|
|
A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
|
|
A("bfi %[bin],%[work],#4,#1") /* Store read bit as the bit 4 */
|
|
|
|
/* bit 3 */
|
|
A("str %[sck_mask],[%[sck_port]]") /* SODR */
|
|
A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
|
|
A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
|
|
A("bfi %[bin],%[work],#3,#1") /* Store read bit as the bit 3 */
|
|
|
|
/* bit 2 */
|
|
A("str %[sck_mask],[%[sck_port]]") /* SODR */
|
|
A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
|
|
A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
|
|
A("bfi %[bin],%[work],#2,#1") /* Store read bit as the bit 2 */
|
|
|
|
/* bit 1 */
|
|
A("str %[sck_mask],[%[sck_port]]") /* SODR */
|
|
A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
|
|
A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
|
|
A("bfi %[bin],%[work],#1,#1") /* Store read bit as the bit 1 */
|
|
|
|
/* bit 0 */
|
|
A("str %[sck_mask],[%[sck_port]]") /* SODR */
|
|
A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
|
|
A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
|
|
A("bfi %[bin],%[work],#0,#1") /* Store read bit as the bit 0 */
|
|
|
|
A("subs %[todo],#1") /* Decrement count of pending words to send, update status */
|
|
A("strb.w %[bin], [%[ptr]], #1") /* Store read value into buffer, increment buffer pointer */
|
|
A("bne.n loop%=") /* Repeat until done */
|
|
|
|
: [ptr]"+r"(ptr),
|
|
[todo]"+r"(todo),
|
|
[bin]"+r"(bin),
|
|
[work]"+r"(work)
|
|
: [bitband_miso_port]"r"( BITBAND_MISO_PORT ),
|
|
[sck_mask]"r"( SCK_MASK ),
|
|
[sck_port]"r"( SCK_PORT_PLUS30 )
|
|
: "cc"
|
|
);
|
|
}
|
|
|
|
static void spiTxBlockX(const uint8_t* buf, uint32_t todo) {
|
|
do {
|
|
(void) spiTransferTx(*buf++);
|
|
} while (--todo);
|
|
}
|
|
|
|
static void spiRxBlockX(uint8_t* buf, uint32_t todo) {
|
|
do {
|
|
*buf++ = spiTransferRx(0xFF);
|
|
} while (--todo);
|
|
}
|
|
|
|
// Pointers to generic functions for block tranfers
|
|
static pfnSpiTxBlock spiTxBlock = spiTxBlockX;
|
|
static pfnSpiRxBlock spiRxBlock = spiRxBlockX;
|
|
|
|
#if MB(ALLIGATOR) // control SDSS pin
|
|
void spiBegin() {
|
|
SET_OUTPUT(SS_PIN);
|
|
WRITE(SS_PIN, HIGH);
|
|
SET_OUTPUT(SCK_PIN);
|
|
SET_INPUT(MISO_PIN);
|
|
SET_OUTPUT(MOSI_PIN);
|
|
}
|
|
|
|
uint8_t spiRec() {
|
|
WRITE(SS_PIN, LOW);
|
|
WRITE(MOSI_PIN, 1); /* Output 1s 1*/
|
|
uint8_t b = spiTransferRx(0xFF);
|
|
WRITE(SS_PIN, HIGH);
|
|
return b;
|
|
}
|
|
|
|
void spiRead(uint8_t* buf, uint16_t nbyte) {
|
|
uint32_t todo = nbyte;
|
|
if (todo == 0) return;
|
|
|
|
WRITE(SS_PIN, LOW);
|
|
WRITE(MOSI_PIN, 1); /* Output 1s 1*/
|
|
spiRxBlock(buf,nbyte);
|
|
WRITE(SS_PIN, HIGH);
|
|
}
|
|
|
|
void spiSend(uint8_t b) {
|
|
WRITE(SS_PIN, LOW);
|
|
(void) spiTransferTx(b);
|
|
WRITE(SS_PIN, HIGH);
|
|
}
|
|
|
|
void spiSendBlock(uint8_t token, const uint8_t* buf) {
|
|
WRITE(SS_PIN, LOW);
|
|
(void) spiTransferTx(token);
|
|
spiTxBlock(buf,512);
|
|
WRITE(SS_PIN, HIGH);
|
|
|
|
#else // let calling routine control SDSS
|
|
void spiBegin() {
|
|
SET_OUTPUT(SS_PIN);
|
|
SET_OUTPUT(SCK_PIN);
|
|
SET_INPUT(MISO_PIN);
|
|
SET_OUTPUT(MOSI_PIN);
|
|
}
|
|
|
|
uint8_t spiRec() {
|
|
WRITE(MOSI_PIN, 1); /* Output 1s 1*/
|
|
uint8_t b = spiTransferRx(0xFF);
|
|
return b;
|
|
}
|
|
|
|
void spiRead(uint8_t* buf, uint16_t nbyte) {
|
|
uint32_t todo = nbyte;
|
|
if (todo == 0) return;
|
|
|
|
WRITE(MOSI_PIN, 1); /* Output 1s 1*/
|
|
spiRxBlock(buf,nbyte);
|
|
}
|
|
|
|
void spiSend(uint8_t b) {
|
|
(void) spiTransferTx(b);
|
|
}
|
|
|
|
void spiSendBlock(uint8_t token, const uint8_t* buf) {
|
|
(void) spiTransferTx(token);
|
|
spiTxBlock(buf,512);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
/**
|
|
* spiRate should be
|
|
* 0 : 8 - 10 MHz
|
|
* 1 : 4 - 5 MHz
|
|
* 2 : 2 - 2.5 MHz
|
|
* 3 : 1 - 1.25 MHz
|
|
* 4 : 500 - 625 kHz
|
|
* 5 : 250 - 312 kHz
|
|
* 6 : 125 - 156 kHz
|
|
*/
|
|
void spiInit(uint8_t spiRate) {
|
|
switch (spiRate) {
|
|
case 0:
|
|
spiTransferTx = spiTransferTx0;
|
|
spiTransferRx = spiTransferRx0;
|
|
spiTxBlock = spiTxBlock0;
|
|
spiRxBlock = spiRxBlock0;
|
|
break;
|
|
case 1:
|
|
spiTransferTx = spiTransfer1;
|
|
spiTransferRx = spiTransfer1;
|
|
spiTxBlock = spiTxBlockX;
|
|
spiRxBlock = spiRxBlockX;
|
|
break;
|
|
default:
|
|
spiDelayCyclesX4 = (F_CPU/1000000) >> (6 - spiRate);
|
|
spiTransferTx = spiTransferX;
|
|
spiTransferRx = spiTransferX;
|
|
spiTxBlock = spiTxBlockX;
|
|
spiRxBlock = spiRxBlockX;
|
|
break;
|
|
}
|
|
|
|
#if MB(ALLIGATOR)
|
|
WRITE(SS_PIN, HIGH);
|
|
#endif
|
|
WRITE(MOSI_PIN, HIGH);
|
|
WRITE(SCK_PIN, LOW);
|
|
}
|
|
|
|
/** Begin SPI transaction, set clock, bit order, data mode */
|
|
void spiBeginTransaction(uint32_t spiClock, uint8_t bitOrder, uint8_t dataMode) {
|
|
// TODO: to be implemented
|
|
}
|
|
|
|
#pragma GCC reset_options
|
|
|
|
#else
|
|
|
|
#if MB(ALLIGATOR)
|
|
|
|
// slave selects controlled by SPI controller
|
|
// doesn't support changing SPI speeds for SD card
|
|
|
|
// --------------------------------------------------------------------------
|
|
// hardware SPI
|
|
// --------------------------------------------------------------------------
|
|
// 8.4 MHz, 4 MHz, 2 MHz, 1 MHz, 0.5 MHz, 0.329 MHz, 0.329 MHz
|
|
int spiDueDividors[] = { 10, 21, 42, 84, 168, 255, 255 };
|
|
bool spiInitMaded = false;
|
|
|
|
void spiBegin() {
|
|
if (spiInitMaded == false) {
|
|
// Configure SPI pins
|
|
PIO_Configure(
|
|
g_APinDescription[SCK_PIN].pPort,
|
|
g_APinDescription[SCK_PIN].ulPinType,
|
|
g_APinDescription[SCK_PIN].ulPin,
|
|
g_APinDescription[SCK_PIN].ulPinConfiguration);
|
|
PIO_Configure(
|
|
g_APinDescription[MOSI_PIN].pPort,
|
|
g_APinDescription[MOSI_PIN].ulPinType,
|
|
g_APinDescription[MOSI_PIN].ulPin,
|
|
g_APinDescription[MOSI_PIN].ulPinConfiguration);
|
|
PIO_Configure(
|
|
g_APinDescription[MISO_PIN].pPort,
|
|
g_APinDescription[MISO_PIN].ulPinType,
|
|
g_APinDescription[MISO_PIN].ulPin,
|
|
g_APinDescription[MISO_PIN].ulPinConfiguration);
|
|
|
|
// set master mode, peripheral select, fault detection
|
|
SPI_Configure(SPI0, ID_SPI0, SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PS);
|
|
SPI_Enable(SPI0);
|
|
|
|
#if MB(ALLIGATOR)
|
|
SET_OUTPUT(DAC0_SYNC);
|
|
#if EXTRUDERS > 1
|
|
SET_OUTPUT(DAC1_SYNC);
|
|
WRITE(DAC1_SYNC, HIGH);
|
|
#endif
|
|
SET_OUTPUT(SPI_EEPROM1_CS);
|
|
SET_OUTPUT(SPI_EEPROM2_CS);
|
|
SET_OUTPUT(SPI_FLASH_CS);
|
|
WRITE(DAC0_SYNC, HIGH);
|
|
WRITE(SPI_EEPROM1_CS, HIGH );
|
|
WRITE(SPI_EEPROM2_CS, HIGH );
|
|
WRITE(SPI_FLASH_CS, HIGH );
|
|
WRITE(SS_PIN, HIGH );
|
|
#endif // MB(ALLIGATOR)
|
|
|
|
OUT_WRITE(SDSS,0);
|
|
|
|
PIO_Configure(
|
|
g_APinDescription[SPI_PIN].pPort,
|
|
g_APinDescription[SPI_PIN].ulPinType,
|
|
g_APinDescription[SPI_PIN].ulPin,
|
|
g_APinDescription[SPI_PIN].ulPinConfiguration);
|
|
|
|
spiInit(1);
|
|
spiInitMaded = true;
|
|
}
|
|
}
|
|
|
|
void spiInit(uint8_t spiRate) {
|
|
if (spiInitMaded == false) {
|
|
if (spiRate > 6) spiRate = 1;
|
|
|
|
#if MB(ALLIGATOR)
|
|
// Set SPI mode 1, clock, select not active after transfer, with delay between transfers
|
|
SPI_ConfigureNPCS(SPI0, SPI_CHAN_DAC,
|
|
SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDueDividors[spiRate]) |
|
|
SPI_CSR_DLYBCT(1));
|
|
// Set SPI mode 0, clock, select not active after transfer, with delay between transfers
|
|
SPI_ConfigureNPCS(SPI0, SPI_CHAN_EEPROM1, SPI_CSR_NCPHA |
|
|
SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDueDividors[spiRate]) |
|
|
SPI_CSR_DLYBCT(1));
|
|
#endif//MB(ALLIGATOR)
|
|
|
|
// Set SPI mode 0, clock, select not active after transfer, with delay between transfers
|
|
SPI_ConfigureNPCS(SPI0, SPI_CHAN, SPI_CSR_NCPHA |
|
|
SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDueDividors[spiRate]) |
|
|
SPI_CSR_DLYBCT(1));
|
|
SPI_Enable(SPI0);
|
|
spiInitMaded = true;
|
|
}
|
|
}
|
|
|
|
// Write single byte to SPI
|
|
void spiSend(byte b) {
|
|
// write byte with address and end transmission flag
|
|
SPI0->SPI_TDR = (uint32_t)b | SPI_PCS(SPI_CHAN) | SPI_TDR_LASTXFER;
|
|
// wait for transmit register empty
|
|
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
|
// wait for receive register
|
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
|
// clear status
|
|
SPI0->SPI_RDR;
|
|
//delayMicroseconds(1U);
|
|
}
|
|
|
|
void spiSend(const uint8_t* buf, size_t n) {
|
|
if (n == 0) return;
|
|
for (size_t i = 0; i < n - 1; i++) {
|
|
SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(SPI_CHAN);
|
|
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
|
SPI0->SPI_RDR;
|
|
//delayMicroseconds(1U);
|
|
}
|
|
spiSend(buf[n - 1]);
|
|
}
|
|
|
|
void spiSend(uint32_t chan, byte b) {
|
|
uint8_t dummy_read = 0;
|
|
// wait for transmit register empty
|
|
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
|
// write byte with address and end transmission flag
|
|
SPI0->SPI_TDR = (uint32_t)b | SPI_PCS(chan) | SPI_TDR_LASTXFER;
|
|
// wait for receive register
|
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
|
// clear status
|
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1)
|
|
dummy_read = SPI0->SPI_RDR;
|
|
UNUSED(dummy_read);
|
|
}
|
|
|
|
void spiSend(uint32_t chan, const uint8_t* buf, size_t n) {
|
|
uint8_t dummy_read = 0;
|
|
if (n == 0) return;
|
|
for (int i = 0; i < (int)n - 1; i++) {
|
|
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
|
SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(chan);
|
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1)
|
|
dummy_read = SPI0->SPI_RDR;
|
|
UNUSED(dummy_read);
|
|
}
|
|
spiSend(chan, buf[n - 1]);
|
|
}
|
|
|
|
// Read single byte from SPI
|
|
uint8_t spiRec() {
|
|
// write dummy byte with address and end transmission flag
|
|
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN) | SPI_TDR_LASTXFER;
|
|
// wait for transmit register empty
|
|
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
|
|
|
// wait for receive register
|
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
|
// get byte from receive register
|
|
//delayMicroseconds(1U);
|
|
return SPI0->SPI_RDR;
|
|
}
|
|
|
|
uint8_t spiRec(uint32_t chan) {
|
|
uint8_t spirec_tmp;
|
|
// wait for transmit register empty
|
|
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1)
|
|
spirec_tmp = SPI0->SPI_RDR;
|
|
UNUSED(spirec_tmp);
|
|
|
|
// write dummy byte with address and end transmission flag
|
|
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(chan) | SPI_TDR_LASTXFER;
|
|
|
|
// wait for receive register
|
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
|
// get byte from receive register
|
|
return SPI0->SPI_RDR;
|
|
}
|
|
|
|
// Read from SPI into buffer
|
|
void spiRead(uint8_t* buf, uint16_t nbyte) {
|
|
if (nbyte-- == 0) return;
|
|
|
|
for (int i = 0; i < nbyte; i++) {
|
|
//while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
|
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN);
|
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
|
buf[i] = SPI0->SPI_RDR;
|
|
//delayMicroseconds(1U);
|
|
}
|
|
buf[nbyte] = spiRec();
|
|
}
|
|
|
|
// Write from buffer to SPI
|
|
void spiSendBlock(uint8_t token, const uint8_t* buf) {
|
|
SPI0->SPI_TDR = (uint32_t)token | SPI_PCS(SPI_CHAN);
|
|
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
|
//while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
|
//SPI0->SPI_RDR;
|
|
for (int i = 0; i < 511; i++) {
|
|
SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(SPI_CHAN);
|
|
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
|
SPI0->SPI_RDR;
|
|
//delayMicroseconds(1U);
|
|
}
|
|
spiSend(buf[511]);
|
|
}
|
|
|
|
/** Begin SPI transaction, set clock, bit order, data mode */
|
|
void spiBeginTransaction(uint32_t spiClock, uint8_t bitOrder, uint8_t dataMode) {
|
|
// TODO: to be implemented
|
|
}
|
|
|
|
#else // U8G compatible hardware SPI
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#define SPI_MODE_0_DUE_HW 2 // DUE CPHA control bit is inverted
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#define SPI_MODE_1_DUE_HW 3
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#define SPI_MODE_2_DUE_HW 0
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#define SPI_MODE_3_DUE_HW 1
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void spiInit(uint8_t spiRate=6) { // Default to slowest rate if not specified)
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// 8.4 MHz, 4 MHz, 2 MHz, 1 MHz, 0.5 MHz, 0.329 MHz, 0.329 MHz
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int spiDueDividors[] = { 10, 21, 42, 84, 168, 255, 255 };
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if (spiRate > 6) spiRate = 1;
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// Enable PIOA and SPI0
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REG_PMC_PCER0 = (1UL << ID_PIOA) | (1UL << ID_SPI0);
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// Disable PIO on A26 and A27
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REG_PIOA_PDR = 0x0C000000;
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OUT_WRITE(SDSS, 1);
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// Reset SPI0 (from sam lib)
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SPI0->SPI_CR = SPI_CR_SPIDIS;
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SPI0->SPI_CR = SPI_CR_SWRST;
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SPI0->SPI_CR = SPI_CR_SWRST;
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SPI0->SPI_CR = SPI_CR_SPIEN;
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// TMC2103 compatible setup
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// Master mode, no fault detection, PCS bits in data written to TDR select CSR register
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SPI0->SPI_MR = SPI_MR_MSTR | SPI_MR_PS | SPI_MR_MODFDIS;
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// SPI mode 0, 8 Bit data transfer, baud rate
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SPI0->SPI_CSR[3] = SPI_CSR_SCBR(spiDueDividors[spiRate]) | SPI_CSR_CSAAT | SPI_MODE_0_DUE_HW; // use same CSR as TMC2130
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}
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static uint8_t spiTransfer(uint8_t data) {
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// Wait until tx register is empty
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while( (SPI0->SPI_SR & SPI_SR_TDRE) == 0 );
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// Send data
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SPI0->SPI_TDR = (uint32_t)data | 0x00070000UL; // Add TMC2130 PCS bits to every byte
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// wait for transmit register empty
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while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
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// wait for receive register
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while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
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// get byte from receive register
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return SPI0->SPI_RDR;
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}
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void spiBegin() {
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spiInit();
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}
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uint8_t spiRec() {
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uint8_t data = spiTransfer(0xFF);
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return data;
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}
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void spiRead(uint8_t* buf, uint16_t nbyte) {
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if (nbyte == 0) return;
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for (int i = 0; i < nbyte; i++)
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buf[i] = spiTransfer(0xFF);
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}
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void spiSend(uint8_t data) {
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spiTransfer(data);
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}
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void spiSend(const uint8_t* buf, size_t n) {
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if (n == 0) return;
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for (uint16_t i = 0; i < n; i++)
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spiTransfer(buf[i]);
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}
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void spiSendBlock(uint8_t token, const uint8_t* buf) {
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spiTransfer(token);
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for (uint16_t i = 0; i < 512; i++)
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spiTransfer(buf[i]);
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}
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#endif //MB(ALLIGATOR)
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#endif // ENABLED(SOFTWARE_SPI)
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#endif // ARDUINO_ARCH_SAM
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