Commit graph

14 commits

Author SHA1 Message Date
Scott Lahteine 0feeef2604 Update copyright in headers 2019-02-12 15:30:11 -06:00
Scott Lahteine 5580773191
Use FastIO, sanity-check LPC SD options, apply formatting (#12231) 2018-10-26 15:23:02 -05:00
Sam Lane d783400330 Updates to STM32F7 HAL, for completeness (#11770) 2018-09-09 03:26:15 -05:00
Scott Lahteine 6a3207391f Remove obsolete HAL_timer_restrain 2018-08-31 16:17:22 -05:00
Scott Lahteine 0987ed2a18 Use American English 2018-08-22 17:16:18 -05:00
etagle 0566badcef Add memory barrier, optimal interrupt on-off
Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)
2018-05-20 02:39:34 -05:00
Chris Pepper cc6d41e1d3 Use a macro for HAL header redirection (#10380) 2018-04-12 20:25:08 -05:00
Scott Lahteine 98d48fc731 Followup to HAL_timer_restrain
Followup to #9985
2018-03-07 22:18:37 -06:00
Scott Lahteine d45f19d385 Remove Unicode from var name 2018-03-07 19:08:44 -06:00
Chris Pepper a1a88ebabc HAL function to ensure min stepper interrupt interval (#9985) 2018-03-07 17:53:25 -06:00
Scott Lahteine a810e585db Drop HAL_timer_set_count 2018-02-20 03:10:39 -06:00
Scott Lahteine 03d790451f
[2.0.x] HAL timer set/get count => set/get compare (#9581)
To reduce confusion over the current timer count vs. the compare (aka "top") value. Caution: this re-uses the function name, changing its meaning.
2018-02-10 20:42:00 -06:00
Scott Lahteine 42933c804a Cleanups for STM32F7 2018-01-15 02:46:37 -06:00
Morten a0246c5c96 Add support for STM32F7 MCU 2018-01-15 01:13:03 -06:00