Scott Lahteine
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0feeef2604
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Update copyright in headers
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2019-02-12 15:30:11 -06:00 |
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mr-miky
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11c7945365
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Don't include STM32 Core code when compiling STM32 Generic (#12575)
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2018-12-03 06:55:49 -06:00 |
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Karl Andersson
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8b5e51c9aa
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STM32F4xx modifications for HAL_STM32 (#12080)
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2018-10-16 06:42:41 -05:00 |
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Scott Lahteine
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0987ed2a18
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Use American English
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2018-08-22 17:16:18 -05:00 |
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Karl Andersson
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e0276d2f32
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Official STMicroelectronics Arduino Core STM32F4 HAL compatibility (#11006)
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2018-06-12 18:38:00 -05:00 |
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etagle
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0566badcef
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Add memory barrier, optimal interrupt on-off
Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)
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2018-05-20 02:39:34 -05:00 |
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Karl Andersson
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428c54f2ad
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[2.0.x] HAL for STM32F4 (#10434)
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2018-04-17 17:33:29 -05:00 |
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