0566badcef
Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/) |
||
|---|---|---|
| .. | ||
| lib | ||
| src | ||
| Configuration.h | ||
| Configuration_adv.h | ||
| Makefile | ||
| Marlin.ino | ||